Index: src/IceTargetLoweringARM32.h |
diff --git a/src/IceTargetLoweringARM32.h b/src/IceTargetLoweringARM32.h |
index 62a903ded6cc37e43ae0695e5d1ea77c78b9a223..631060f1d9ce2a7756979cb8c3e7f65d3e9df770 100644 |
--- a/src/IceTargetLoweringARM32.h |
+++ b/src/IceTargetLoweringARM32.h |
@@ -48,6 +48,9 @@ private: |
ARM32InstructionSet InstructionSet = ARM32InstructionSet::Begin; |
}; |
+// Extend enum RegClass with ARM32-specific register classes (if any). |
+enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target }; |
John
2015/11/09 16:23:29
This belongs in the IceRegistersARM32.h file, righ
Jim Stichnoth
2015/11/09 18:45:35
Done (for MIPS too).
|
+ |
// The target lowering logic for ARM32. |
class TargetARM32 : public TargetLowering { |
TargetARM32() = delete; |
@@ -74,8 +77,11 @@ public: |
IceString getRegName(SizeT RegNum, Type Ty) const override; |
llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
RegSetMask Exclude) const override; |
- const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { |
- return TypeToRegisterSet[Ty]; |
+ const llvm::SmallBitVector & |
+ getRegistersForClass(const Variable *Var) const override { |
John
2015/11/09 16:23:29
This method should be renamed to, e.g., getRegiste
Jim Stichnoth
2015/11/09 18:45:35
Done.
|
+ RegClass RC = Var->getRegClass(); |
+ assert(RC < RC_Target); |
+ return TypeToRegisterSet[RC]; |
} |
const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
return RegisterAliases[Reg]; |
@@ -554,7 +560,7 @@ protected: |
bool MaybeLeafFunc = true; |
size_t SpillAreaSizeBytes = 0; |
// TODO(jpp): std::array instead of array. |
- static llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; |
+ static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM]; |
static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM]; |
static llvm::SmallBitVector ScratchRegs; |
llvm::SmallBitVector RegsUsed; |