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Side by Side Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 1427973003: Subzero: Refactor x86 register representation to actively use aliases. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Reformat Created 5 years, 1 month ago
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1 ; This tries to be a comprehensive test of i64 operations, in 1 ; This tries to be a comprehensive test of i64 operations, in
2 ; particular the patterns for lowering i64 operations into constituent 2 ; particular the patterns for lowering i64 operations into constituent
3 ; i32 operations on x86-32. 3 ; i32 operations on x86-32.
4 4
5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ 6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
7 ; RUN: | %if --need=target_X8632 --command FileCheck %s 7 ; RUN: | %if --need=target_X8632 --command FileCheck %s
8 8
9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ 10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
(...skipping 708 matching lines...) Expand 10 before | Expand all | Expand 10 after
719 entry: 719 entry:
720 %conv = trunc i64 %a to i16 720 %conv = trunc i64 %a to i16
721 %conv.ret_ext = sext i16 %conv to i32 721 %conv.ret_ext = sext i16 %conv to i32
722 ret i32 %conv.ret_ext 722 ret i32 %conv.ret_ext
723 } 723 }
724 ; CHECK-LABEL: trunc64To16Signed 724 ; CHECK-LABEL: trunc64To16Signed
725 ; CHECK: mov eax,DWORD PTR [esp+0x4] 725 ; CHECK: mov eax,DWORD PTR [esp+0x4]
726 ; CHECK-NEXT: movsx eax,ax 726 ; CHECK-NEXT: movsx eax,ax
727 ; 727 ;
728 ; OPTM1-LABEL: trunc64To16Signed 728 ; OPTM1-LABEL: trunc64To16Signed
729 ; OPTM1: mov eax,DWORD PTR [esp+ 729 ; OPTM1: mov ax,WORD PTR [esp+
730 ; OPTM1: movsx eax, 730 ; OPTM1: movsx eax,
731 731
732 ; ARM32-LABEL: trunc64To16Signed 732 ; ARM32-LABEL: trunc64To16Signed
733 ; ARM32: sxth r0, r0 733 ; ARM32: sxth r0, r0
734 734
735 define internal i32 @trunc64To8Signed(i64 %a) { 735 define internal i32 @trunc64To8Signed(i64 %a) {
736 entry: 736 entry:
737 %conv = trunc i64 %a to i8 737 %conv = trunc i64 %a to i8
738 %conv.ret_ext = sext i8 %conv to i32 738 %conv.ret_ext = sext i8 %conv to i32
739 ret i32 %conv.ret_ext 739 ret i32 %conv.ret_ext
(...skipping 61 matching lines...) Expand 10 before | Expand all | Expand 10 after
801 entry: 801 entry:
802 %conv = trunc i64 %a to i16 802 %conv = trunc i64 %a to i16
803 %conv.ret_ext = zext i16 %conv to i32 803 %conv.ret_ext = zext i16 %conv to i32
804 ret i32 %conv.ret_ext 804 ret i32 %conv.ret_ext
805 } 805 }
806 ; CHECK-LABEL: trunc64To16Unsigned 806 ; CHECK-LABEL: trunc64To16Unsigned
807 ; CHECK: mov eax,DWORD PTR [esp+0x4] 807 ; CHECK: mov eax,DWORD PTR [esp+0x4]
808 ; CHECK-NEXT: movzx eax,ax 808 ; CHECK-NEXT: movzx eax,ax
809 ; 809 ;
810 ; OPTM1-LABEL: trunc64To16Unsigned 810 ; OPTM1-LABEL: trunc64To16Unsigned
811 ; OPTM1: mov eax,DWORD PTR [esp+ 811 ; OPTM1: mov ax,WORD PTR [esp+
812 ; OPTM1: movzx eax, 812 ; OPTM1: movzx eax,
813 813
814 ; ARM32-LABEL: trunc64To16Unsigned 814 ; ARM32-LABEL: trunc64To16Unsigned
815 ; ARM32: uxth 815 ; ARM32: uxth
816 816
817 define internal i32 @trunc64To8Unsigned(i64 %a) { 817 define internal i32 @trunc64To8Unsigned(i64 %a) {
818 entry: 818 entry:
819 %conv = trunc i64 %a to i8 819 %conv = trunc i64 %a to i8
820 %conv.ret_ext = zext i8 %conv to i32 820 %conv.ret_ext = zext i8 %conv to i32
821 ret i32 %conv.ret_ext 821 ret i32 %conv.ret_ext
(...skipping 11 matching lines...) Expand all
833 833
834 define internal i32 @trunc64To1(i64 %a) { 834 define internal i32 @trunc64To1(i64 %a) {
835 entry: 835 entry:
836 ; %tobool = icmp ne i64 %a, 0 836 ; %tobool = icmp ne i64 %a, 0
837 %tobool = trunc i64 %a to i1 837 %tobool = trunc i64 %a to i1
838 %tobool.ret_ext = zext i1 %tobool to i32 838 %tobool.ret_ext = zext i1 %tobool to i32
839 ret i32 %tobool.ret_ext 839 ret i32 %tobool.ret_ext
840 } 840 }
841 ; CHECK-LABEL: trunc64To1 841 ; CHECK-LABEL: trunc64To1
842 ; CHECK: mov eax,DWORD PTR [esp+0x4] 842 ; CHECK: mov eax,DWORD PTR [esp+0x4]
843 ; CHECK: and eax,0x1 843 ; CHECK: and al,0x1
844 ; CHECK-NOT: and eax,0x1 844 ; CHECK-NOT: and eax,0x1
845 ; 845 ;
846 ; OPTM1-LABEL: trunc64To1 846 ; OPTM1-LABEL: trunc64To1
847 ; OPTM1: mov eax,DWORD PTR [esp+ 847 ; OPTM1: mov eax,DWORD PTR [esp+
848 ; OPTM1: and eax,0x1 848 ; OPTM1: and al,0x1
849 ; OPTM1-NOT: and eax,0x1 849 ; OPTM1-NOT: and eax,0x1
850 850
851 ; ARM32-LABEL: trunc64To1 851 ; ARM32-LABEL: trunc64To1
852 ; ARM32-OM1: and r0, r0, #1 852 ; ARM32-OM1: and r0, r0, #1
853 ; ARM32-OM1: and r0, r0, #1 853 ; ARM32-OM1: and r0, r0, #1
854 ; ARM32-O2: tst r0, #1 854 ; ARM32-O2: tst r0, #1
855 ; ARM32-O2: moveq [[RES:r[0-9]+]], #0 855 ; ARM32-O2: moveq [[RES:r[0-9]+]], #0
856 ; ARM32-O2: movne [[RES]], #1 856 ; ARM32-O2: movne [[RES]], #1
857 857
858 define internal i64 @sext32To64(i32 %a) { 858 define internal i64 @sext32To64(i32 %a) {
(...skipping 1024 matching lines...) Expand 10 before | Expand all | Expand 10 after
1883 ; CHECK-LABEL: phi64Undef 1883 ; CHECK-LABEL: phi64Undef
1884 ; CHECK: mov {{.*}},0x0 1884 ; CHECK: mov {{.*}},0x0
1885 ; CHECK: mov {{.*}},0x0 1885 ; CHECK: mov {{.*}},0x0
1886 ; OPTM1-LABEL: phi64Undef 1886 ; OPTM1-LABEL: phi64Undef
1887 ; OPTM1: mov {{.*}},0x0 1887 ; OPTM1: mov {{.*}},0x0
1888 ; OPTM1: mov {{.*}},0x0 1888 ; OPTM1: mov {{.*}},0x0
1889 ; ARM32-LABEL: phi64Undef 1889 ; ARM32-LABEL: phi64Undef
1890 ; ARM32: mov {{.*}} #0 1890 ; ARM32: mov {{.*}} #0
1891 ; ARM32: mov {{.*}} #0 1891 ; ARM32: mov {{.*}} #0
1892 1892
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