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| 1 //===- subzero/src/IceTargetLoweringX86RegClass.h - x86 reg class -*- C++ -*-=// |
| 2 // |
| 3 // The Subzero Code Generator |
| 4 // |
| 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. |
| 7 // |
| 8 //===----------------------------------------------------------------------===// |
| 9 /// |
| 10 /// \file |
| 11 /// This file declares the X86 register class extensions. |
| 12 /// |
| 13 //===----------------------------------------------------------------------===// |
| 14 |
| 15 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H |
| 16 #define SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H |
| 17 |
| 18 #include "IceOperand.h" // RC_Target |
| 19 |
| 20 namespace Ice { |
| 21 namespace X86Internal { |
| 22 |
| 23 // Extend enum RegClass with x86-specific register classes. |
| 24 enum RegClassX86 : uint8_t { |
| 25 RCX86_Is64To8 = RC_Target, // 64-bit GPR trivially truncable to 8-bit |
| 26 RCX86_Is32To8, // 32-bit GPR trivially truncable to 8-bit |
| 27 RCX86_Is16To8, // 16-bit GPR trivially truncable to 8-bit |
| 28 RCX86_IsTrunc8Rcvr, // 8-bit GPR that can receive a trunc operation |
| 29 RCX86_IsAhRcvr, // 8-bit GPR that can be a mov dest from %ah |
| 30 RCX86_NUM |
| 31 }; |
| 32 |
| 33 } // end of namespace X86Internal |
| 34 } // end of namespace Ice |
| 35 |
| 36 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H |
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