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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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35 | 35 |
36 void translateOm1() override; | 36 void translateOm1() override; |
37 void translateO2() override; | 37 void translateO2() override; |
38 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; | 38 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; |
39 | 39 |
40 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } | 40 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } |
41 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 41 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
42 IceString getRegName(SizeT RegNum, Type Ty) const override; | 42 IceString getRegName(SizeT RegNum, Type Ty) const override; |
43 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 43 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
44 RegSetMask Exclude) const override; | 44 RegSetMask Exclude) const override; |
45 const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { | 45 const llvm::SmallBitVector & |
46 return TypeToRegisterSet[Ty]; | 46 getRegistersForVariable(const Variable *Var) const override { |
| 47 RegClass RC = Var->getRegClass(); |
| 48 assert(RC < RC_Target); |
| 49 return TypeToRegisterSet[RC]; |
47 } | 50 } |
48 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 51 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
49 return RegisterAliases[Reg]; | 52 return RegisterAliases[Reg]; |
50 } | 53 } |
51 bool hasFramePointer() const override { return UsesFramePointer; } | 54 bool hasFramePointer() const override { return UsesFramePointer; } |
52 void setHasFramePointer() override { UsesFramePointer = true; } | 55 void setHasFramePointer() override { UsesFramePointer = true; } |
53 SizeT getStackReg() const override { return RegMIPS32::Reg_SP; } | 56 SizeT getStackReg() const override { return RegMIPS32::Reg_SP; } |
54 SizeT getFrameOrStackReg() const override { | 57 SizeT getFrameOrStackReg() const override { |
55 return UsesFramePointer ? RegMIPS32::Reg_FP : RegMIPS32::Reg_SP; | 58 return UsesFramePointer ? RegMIPS32::Reg_FP : RegMIPS32::Reg_SP; |
56 } | 59 } |
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224 void doAddressOptStore() override; | 227 void doAddressOptStore() override; |
225 void randomlyInsertNop(float Probability, | 228 void randomlyInsertNop(float Probability, |
226 RandomNumberGenerator &RNG) override; | 229 RandomNumberGenerator &RNG) override; |
227 void | 230 void |
228 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, | 231 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, |
229 const llvm::SmallBitVector &ExcludeRegisters, | 232 const llvm::SmallBitVector &ExcludeRegisters, |
230 uint64_t Salt) const override; | 233 uint64_t Salt) const override; |
231 | 234 |
232 bool UsesFramePointer = false; | 235 bool UsesFramePointer = false; |
233 bool NeedsStackAlignment = false; | 236 bool NeedsStackAlignment = false; |
234 static llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; | 237 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; |
235 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; | 238 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; |
236 static llvm::SmallBitVector ScratchRegs; | 239 static llvm::SmallBitVector ScratchRegs; |
237 llvm::SmallBitVector RegsUsed; | 240 llvm::SmallBitVector RegsUsed; |
238 VarList PhysicalRegisters[IceType_NUM]; | 241 VarList PhysicalRegisters[IceType_NUM]; |
239 | 242 |
240 private: | 243 private: |
241 ~TargetMIPS32() override = default; | 244 ~TargetMIPS32() override = default; |
242 }; | 245 }; |
243 | 246 |
244 class TargetDataMIPS32 final : public TargetDataLowering { | 247 class TargetDataMIPS32 final : public TargetDataLowering { |
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279 protected: | 282 protected: |
280 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 283 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
281 | 284 |
282 private: | 285 private: |
283 ~TargetHeaderMIPS32() = default; | 286 ~TargetHeaderMIPS32() = default; |
284 }; | 287 }; |
285 | 288 |
286 } // end of namespace Ice | 289 } // end of namespace Ice |
287 | 290 |
288 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 291 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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