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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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67 | 67 |
68 void translateOm1() override; | 68 void translateOm1() override; |
69 void translateO2() override; | 69 void translateO2() override; |
70 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; | 70 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; |
71 | 71 |
72 SizeT getNumRegisters() const override { return RegARM32::Reg_NUM; } | 72 SizeT getNumRegisters() const override { return RegARM32::Reg_NUM; } |
73 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 73 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
74 IceString getRegName(SizeT RegNum, Type Ty) const override; | 74 IceString getRegName(SizeT RegNum, Type Ty) const override; |
75 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 75 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
76 RegSetMask Exclude) const override; | 76 RegSetMask Exclude) const override; |
77 const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { | 77 const llvm::SmallBitVector & |
78 return TypeToRegisterSet[Ty]; | 78 getRegistersForVariable(const Variable *Var) const override { |
| 79 RegClass RC = Var->getRegClass(); |
| 80 assert(RC < RC_Target); |
| 81 return TypeToRegisterSet[RC]; |
79 } | 82 } |
80 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 83 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
81 return RegisterAliases[Reg]; | 84 return RegisterAliases[Reg]; |
82 } | 85 } |
83 bool hasFramePointer() const override { return UsesFramePointer; } | 86 bool hasFramePointer() const override { return UsesFramePointer; } |
84 void setHasFramePointer() override { UsesFramePointer = true; } | 87 void setHasFramePointer() override { UsesFramePointer = true; } |
85 SizeT getStackReg() const override { return RegARM32::Reg_sp; } | 88 SizeT getStackReg() const override { return RegARM32::Reg_sp; } |
86 SizeT getFrameOrStackReg() const override { | 89 SizeT getFrameOrStackReg() const override { |
87 return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp; | 90 return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp; |
88 } | 91 } |
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547 /// centered on the given Var's offset plus StackAdjust, and use it. | 550 /// centered on the given Var's offset plus StackAdjust, and use it. |
548 StackVariable *legalizeVariableSlot(Variable *Var, int32_t StackAdjust, | 551 StackVariable *legalizeVariableSlot(Variable *Var, int32_t StackAdjust, |
549 Variable *OrigBaseReg); | 552 Variable *OrigBaseReg); |
550 | 553 |
551 TargetARM32Features CPUFeatures; | 554 TargetARM32Features CPUFeatures; |
552 bool UsesFramePointer = false; | 555 bool UsesFramePointer = false; |
553 bool NeedsStackAlignment = false; | 556 bool NeedsStackAlignment = false; |
554 bool MaybeLeafFunc = true; | 557 bool MaybeLeafFunc = true; |
555 size_t SpillAreaSizeBytes = 0; | 558 size_t SpillAreaSizeBytes = 0; |
556 // TODO(jpp): std::array instead of array. | 559 // TODO(jpp): std::array instead of array. |
557 static llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; | 560 static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM]; |
558 static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM]; | 561 static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM]; |
559 static llvm::SmallBitVector ScratchRegs; | 562 static llvm::SmallBitVector ScratchRegs; |
560 llvm::SmallBitVector RegsUsed; | 563 llvm::SmallBitVector RegsUsed; |
561 VarList PhysicalRegisters[IceType_NUM]; | 564 VarList PhysicalRegisters[IceType_NUM]; |
562 | 565 |
563 /// Helper class that understands the Calling Convention and register | 566 /// Helper class that understands the Calling Convention and register |
564 /// assignments. The first few integer type parameters can use r0-r3, | 567 /// assignments. The first few integer type parameters can use r0-r3, |
565 /// regardless of their position relative to the floating-point/vector | 568 /// regardless of their position relative to the floating-point/vector |
566 /// arguments in the argument list. Floating-point and vector arguments | 569 /// arguments in the argument list. Floating-point and vector arguments |
567 /// can use q0-q3 (aka d0-d7, s0-s15). For more information on the topic, | 570 /// can use q0-q3 (aka d0-d7, s0-s15). For more information on the topic, |
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709 | 712 |
710 private: | 713 private: |
711 ~TargetHeaderARM32() = default; | 714 ~TargetHeaderARM32() = default; |
712 | 715 |
713 TargetARM32Features CPUFeatures; | 716 TargetARM32Features CPUFeatures; |
714 }; | 717 }; |
715 | 718 |
716 } // end of namespace Ice | 719 } // end of namespace Ice |
717 | 720 |
718 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 721 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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