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Side by Side Diff: src/IceTargetLowering.h

Issue 1427973003: Subzero: Refactor x86 register representation to actively use aliases. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Reformat Created 5 years, 1 month ago
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1 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===// 1 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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227 RegSet_CallerSave = 1 << 0, 227 RegSet_CallerSave = 1 << 0,
228 RegSet_CalleeSave = 1 << 1, 228 RegSet_CalleeSave = 1 << 1,
229 RegSet_StackPointer = 1 << 2, 229 RegSet_StackPointer = 1 << 2,
230 RegSet_FramePointer = 1 << 3, 230 RegSet_FramePointer = 1 << 3,
231 RegSet_All = ~RegSet_None 231 RegSet_All = ~RegSet_None
232 }; 232 };
233 using RegSetMask = uint32_t; 233 using RegSetMask = uint32_t;
234 234
235 virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include, 235 virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
236 RegSetMask Exclude) const = 0; 236 RegSetMask Exclude) const = 0;
237 virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const = 0; 237 virtual const llvm::SmallBitVector &
238 getRegistersForVariable(const Variable *Var) const = 0;
238 virtual const llvm::SmallBitVector &getAliasesForRegister(SizeT) const = 0; 239 virtual const llvm::SmallBitVector &getAliasesForRegister(SizeT) const = 0;
239 240
240 void regAlloc(RegAllocKind Kind); 241 void regAlloc(RegAllocKind Kind);
241 242
242 virtual void 243 virtual void
243 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, 244 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
244 const llvm::SmallBitVector &ExcludeRegisters, 245 const llvm::SmallBitVector &ExcludeRegisters,
245 uint64_t Salt) const = 0; 246 uint64_t Salt) const = 0;
246 247
247 /// Save/restore any mutable state for the situation where code emission needs 248 /// Save/restore any mutable state for the situation where code emission needs
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479 virtual void lower() {} 480 virtual void lower() {}
480 481
481 protected: 482 protected:
482 explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {} 483 explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {}
483 GlobalContext *Ctx; 484 GlobalContext *Ctx;
484 }; 485 };
485 486
486 } // end of namespace Ice 487 } // end of namespace Ice
487 488
488 #endif // SUBZERO_SRC_ICETARGETLOWERING_H 489 #endif // SUBZERO_SRC_ICETARGETLOWERING_H
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