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1 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===// | 1 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
11 /// This file declares the registers and their encodings for MIPS32. | 11 /// This file declares the registers and their encodings for MIPS32. |
12 /// | 12 /// |
13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// |
14 | 14 |
15 #ifndef SUBZERO_SRC_ICEREGISTERSMIPS32_H | 15 #ifndef SUBZERO_SRC_ICEREGISTERSMIPS32_H |
16 #define SUBZERO_SRC_ICEREGISTERSMIPS32_H | 16 #define SUBZERO_SRC_ICEREGISTERSMIPS32_H |
17 | 17 |
18 #include "IceDefs.h" | 18 #include "IceDefs.h" |
19 #include "IceInstMIPS32.def" | 19 #include "IceInstMIPS32.def" |
| 20 #include "IceOperand.h" // RC_Target |
20 #include "IceTypes.h" | 21 #include "IceTypes.h" |
21 | 22 |
22 namespace Ice { | 23 namespace Ice { |
23 | 24 |
24 namespace RegMIPS32 { | 25 namespace RegMIPS32 { |
25 | 26 |
26 /// An enum of every register. The enum value may not match the encoding | 27 /// An enum of every register. The enum value may not match the encoding |
27 /// used to binary encode register operands in instructions. | 28 /// used to binary encode register operands in instructions. |
28 enum AllRegisters { | 29 enum AllRegisters { |
29 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 30 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
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52 // TODO(jvoung): Floating point and vector registers... | 53 // TODO(jvoung): Floating point and vector registers... |
53 // Need to model overlap and difference in encoding too. | 54 // Need to model overlap and difference in encoding too. |
54 | 55 |
55 static inline GPRRegister getEncodedGPR(int32_t RegNum) { | 56 static inline GPRRegister getEncodedGPR(int32_t RegNum) { |
56 assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last); | 57 assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last); |
57 return GPRRegister(RegNum - Reg_GPR_First); | 58 return GPRRegister(RegNum - Reg_GPR_First); |
58 } | 59 } |
59 | 60 |
60 } // end of namespace RegMIPS32 | 61 } // end of namespace RegMIPS32 |
61 | 62 |
| 63 // Extend enum RegClass with MIPS32-specific register classes (if any). |
| 64 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target }; |
| 65 |
62 } // end of namespace Ice | 66 } // end of namespace Ice |
63 | 67 |
64 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H | 68 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H |
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