Subzero: Refactor x86 register representation to actively use aliases.

src/IceRegistersMIPS32.h

 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file declares the registers and their encodings for MIPS32.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEREGISTERSMIPS32_H
 #define SUBZERO_SRC_ICEREGISTERSMIPS32_H
 
 #include "IceDefs.h"
 #include "IceInstMIPS32.def"
+#include "IceOperand.h" // RC_Target
 #include "IceTypes.h"
 
 namespace Ice {
 
 namespace RegMIPS32 {
 
 /// An enum of every register. The enum value may not match the encoding
 /// used to binary encode register operands in instructions.
 enum AllRegisters {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
@@ skipping 22 matching lines @@
 // TODO(jvoung): Floating point and vector registers...
 // Need to model overlap and difference in encoding too.
 
 static inline GPRRegister getEncodedGPR(int32_t RegNum) {
   assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last);
   return GPRRegister(RegNum - Reg_GPR_First);
 }
 
 } // end of namespace RegMIPS32
 
+// Extend enum RegClass with MIPS32-specific register classes (if any).
+enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target };
+
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H