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1 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// | 1 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
11 /// This file declares the registers and their encodings for ARM32. | 11 /// This file declares the registers and their encodings for ARM32. |
12 /// | 12 /// |
13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// |
14 | 14 |
15 #ifndef SUBZERO_SRC_ICEREGISTERSARM32_H | 15 #ifndef SUBZERO_SRC_ICEREGISTERSARM32_H |
16 #define SUBZERO_SRC_ICEREGISTERSARM32_H | 16 #define SUBZERO_SRC_ICEREGISTERSARM32_H |
17 | 17 |
18 #include "IceDefs.h" | 18 #include "IceDefs.h" |
19 #include "IceInstARM32.def" | 19 #include "IceInstARM32.def" |
| 20 #include "IceOperand.h" // RC_Target |
20 #include "IceTypes.h" | 21 #include "IceTypes.h" |
21 | 22 |
22 namespace Ice { | 23 namespace Ice { |
23 | 24 |
24 class RegARM32 { | 25 class RegARM32 { |
25 public: | 26 public: |
26 /// An enum of every register. The enum value may not match the encoding used | 27 /// An enum of every register. The enum value may not match the encoding used |
27 /// to binary encode register operands in instructions. | 28 /// to binary encode register operands in instructions. |
28 enum AllRegisters { | 29 enum AllRegisters { |
29 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 30 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
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111 | 112 |
112 static inline QRegister getEncodedQReg(int32_t RegNum) { | 113 static inline QRegister getEncodedQReg(int32_t RegNum) { |
113 assert(Reg_QREG_First <= RegNum); | 114 assert(Reg_QREG_First <= RegNum); |
114 assert(RegNum <= Reg_QREG_Last); | 115 assert(RegNum <= Reg_QREG_Last); |
115 return QRegister(RegNum - Reg_QREG_First); | 116 return QRegister(RegNum - Reg_QREG_First); |
116 } | 117 } |
117 | 118 |
118 static const char *RegNames[]; | 119 static const char *RegNames[]; |
119 }; | 120 }; |
120 | 121 |
| 122 // Extend enum RegClass with ARM32-specific register classes (if any). |
| 123 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target }; |
| 124 |
121 } // end of namespace Ice | 125 } // end of namespace Ice |
122 | 126 |
123 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H | 127 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H |
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