Subzero: Refactor x86 register representation to actively use aliases.

src/IceRegistersARM32.h

 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file declares the registers and their encodings for ARM32.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEREGISTERSARM32_H
 #define SUBZERO_SRC_ICEREGISTERSARM32_H
 
 #include "IceDefs.h"
 #include "IceInstARM32.def"
+#include "IceOperand.h" // RC_Target
 #include "IceTypes.h"
 
 namespace Ice {
 
 class RegARM32 {
 public:
   /// An enum of every register. The enum value may not match the encoding used
   /// to binary encode register operands in instructions.
   enum AllRegisters {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
@@ skipping 81 matching lines @@
 
   static inline QRegister getEncodedQReg(int32_t RegNum) {
     assert(Reg_QREG_First <= RegNum);
     assert(RegNum <= Reg_QREG_Last);
     return QRegister(RegNum - Reg_QREG_First);
   }
 
   static const char *RegNames[];
 };
 
+// Extend enum RegClass with ARM32-specific register classes (if any).
+enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
+
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H