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Issue 1427973003: Subzero: Refactor x86 register representation to actively use aliases. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Reformat Created 5 years, 1 month ago
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1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-32 instructions in the 10 // This file defines properties of lowered x86-32 instructions in the
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
48 /* 8-bit registers */ \ 48 /* 8-bit registers */ \
49 X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 49 X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
50 REGLIST2(RegX8632, eax, ax)) \ 50 REGLIST2(RegX8632, eax, ax)) \
51 X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 51 X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
52 REGLIST2(RegX8632, ecx, cx)) \ 52 REGLIST2(RegX8632, ecx, cx)) \
53 X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 53 X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
54 REGLIST2(RegX8632, edx, dx)) \ 54 REGLIST2(RegX8632, edx, dx)) \
55 X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 55 X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
56 REGLIST2(RegX8632, ebx, bx)) \ 56 REGLIST2(RegX8632, ebx, bx)) \
57 /* High 8-bit registers */ \ 57 /* High 8-bit registers */ \
58 X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 58 X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
59 REGLIST2(RegX8632, eax, ax)) \ 59 REGLIST2(RegX8632, eax, ax)) \
60 X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 60 X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
61 REGLIST2(RegX8632, ecx, cx)) \ 61 REGLIST2(RegX8632, ecx, cx)) \
62 X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 62 X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
63 REGLIST2(RegX8632, edx, dx)) \ 63 REGLIST2(RegX8632, edx, dx)) \
64 X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 64 X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,0,1, \
65 REGLIST2(RegX8632, ebx, bx)) \ 65 REGLIST2(RegX8632, ebx, bx)) \
66 /* End of 8-bit register set */ 66 /* End of 8-bit register set */
67 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 67 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
68 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 68 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
69 // isTrunc8Rcvr, isAhRcvr, aliases) 69 // isTrunc8Rcvr, isAhRcvr, aliases)
70 70
71 #define REGX8632_GPR_TABLE \ 71 #define REGX8632_GPR_TABLE \
72 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 72 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
73 isGPR,is64,is32,is16,is8, isXmm, \ 73 isGPR,is64,is32,is16,is8, isXmm, \
74 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 74 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
(...skipping 130 matching lines...) Expand 10 before | Expand all | Expand 10 after
205 X(Cmpps_lt, "lt") \ 205 X(Cmpps_lt, "lt") \
206 X(Cmpps_le, "le") \ 206 X(Cmpps_le, "le") \
207 X(Cmpps_unord, "unord") \ 207 X(Cmpps_unord, "unord") \
208 X(Cmpps_neq, "neq") \ 208 X(Cmpps_neq, "neq") \
209 X(Cmpps_nlt, "nlt") \ 209 X(Cmpps_nlt, "nlt") \
210 X(Cmpps_nle, "nle") \ 210 X(Cmpps_nle, "nle") \
211 X(Cmpps_ord, "ord") 211 X(Cmpps_ord, "ord")
212 //#define X(val, emit) 212 //#define X(val, emit)
213 213
214 #define ICETYPEX8632_TABLE \ 214 #define ICETYPEX8632_TABLE \
215 /* tag, element type, cvt , sdss, pack, width, fld */ \ 215 /* tag, element type, cvt , sdss, pack, width, fld */ \
216 X(IceType_void, IceType_void, "?", "", "", "", "") \ 216 X(void, void, "?", "", "", "", "") \
217 X(IceType_i1, IceType_void, "si", "", "", "b", "") \ 217 X(i1, void, "si", "", "", "b", "") \
218 X(IceType_i8, IceType_void, "si", "", "", "b", "") \ 218 X(i8, void, "si", "", "", "b", "") \
219 X(IceType_i16, IceType_void, "si", "", "", "w", "") \ 219 X(i16, void, "si", "", "", "w", "") \
220 X(IceType_i32, IceType_void, "si", "", "", "l", "") \ 220 X(i32, void, "si", "", "", "l", "") \
221 X(IceType_i64, IceType_void, "si", "", "", "q", "") \ 221 X(i64, void, "si", "", "", "q", "") \
222 X(IceType_f32, IceType_void, "ss", "ss", "d", "", "s") \ 222 X(f32, void, "ss", "ss", "d", "", "s") \
223 X(IceType_f64, IceType_void, "sd", "sd", "q", "", "l") \ 223 X(f64, void, "sd", "sd", "q", "", "l") \
224 X(IceType_v4i1, IceType_i32, "?", "", "d", "", "") \ 224 X(v4i1, i32, "?", "", "d", "", "") \
225 X(IceType_v8i1, IceType_i16, "?", "", "w", "", "") \ 225 X(v8i1, i16, "?", "", "w", "", "") \
226 X(IceType_v16i1, IceType_i8, "?", "", "b", "", "") \ 226 X(v16i1, i8, "?", "", "b", "", "") \
227 X(IceType_v16i8, IceType_i8, "?", "", "b", "", "") \ 227 X(v16i8, i8, "?", "", "b", "", "") \
228 X(IceType_v8i16, IceType_i16, "?", "", "w", "", "") \ 228 X(v8i16, i16, "?", "", "w", "", "") \
229 X(IceType_v4i32, IceType_i32, "dq", "", "d", "", "") \ 229 X(v4i32, i32, "dq", "", "d", "", "") \
230 X(IceType_v4f32, IceType_f32, "ps", "", "d", "", "") 230 X(v4f32, f32, "ps", "", "d", "", "")
231 //#define X(tag, elementty, cvt, sdss, pack, width, fld) 231 //#define X(tag, elementty, cvt, sdss, pack, width, fld)
232 232
233 #endif // SUBZERO_SRC_ICEINSTX8632_DEF 233 #endif // SUBZERO_SRC_ICEINSTX8632_DEF
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