Fix ARM emit() methods to count instructions generated.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 252 matching lines @@
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
 } // end of anonymous namespace
 
 namespace Ice {
 namespace ARM32 {
 
 size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
                                   const Assembler &Asm) const {
-  static constexpr const size_t FixupSize = sizeof(IValueT);
   if (!BuildDefs::dump())
-    return FixupSize;
+    return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\tmov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
       << RegARM32::RegNames[(Inst >> kRdShift) & 0xF]
       << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
       << "16:" << symbol(Ctx) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
-  return FixupSize;
+  return InstARM32::InstSize;
 }
 
 MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
                                                       const Constant *Value) {
   MoveRelocatableFixup *F =
       new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
   F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
                      : llvm::ELF::R_ARM_MOVT_ABS);
   F->set_value(Value);
   Buffer.installFixup(F);
@@ skipping 59 matching lines @@
     IOffsetT Position = L->getLinkPosition();
     IOffsetT Dest = BoundPc - Position;
     IValueT Inst = Buffer.load<IValueT>(Position);
     Buffer.store<IValueT>(Position, encodeBranchOffset(Dest, Inst));
     L->setPosition(decodeBranchOffset(Inst));
   }
   L->bindTo(BoundPc);
 }
 
 void AssemblerARM32::emitTextInst(const std::string &Text, SizeT InstSize) {
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   AssemblerFixup *F = createTextFixup(Text, InstSize);
   emitFixup(F);
-  for (SizeT I = 0; I < InstSize; ++I)
+  for (SizeT I = 0; I < InstSize; ++I) {
+    AssemblerBuffer::EnsureCapacity ensured(&Buffer);
     Buffer.emit<char>(0);
+  }
 }
 
 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Type,
                                 IValueT Opcode, bool SetCc, IValueT Rn,
                                 IValueT Rd, IValueT Imm12) {
   if (!isGPRRegisterDefined(Rd) || !isConditionDefined(Cond))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (Type << kTypeShift) | (Opcode << kOpcodeShift) |
                            (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
                            (Rd << kRdShift) | Imm12;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitType01(IValueT Opcode, const Operand *OpRd,
                                 const Operand *OpRn, const Operand *OpSrc1,
                                 bool SetFlags, CondARM32::Cond Cond,
                                 Type01Checks RuleChecks) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, RuleChecks);
 }
 
-void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd,
-                                IValueT Rn, const Operand *OpSrc1,
-                                bool SetFlags, CondARM32::Cond Cond,
-                                Type01Checks RuleChecks) {
+void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
+                                const Operand *OpSrc1, bool SetFlags,
+                                CondARM32::Cond Cond, Type01Checks RuleChecks) {
   switch (RuleChecks) {
   case NoChecks:
     break;
   case RdIsPcAndSetFlags:
     if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     break;
   }
 
@@ skipping 560 matching lines @@
   //   tst<c> <Rn>, #<RotatedImm8>
   //
   // cccc00110001nnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, and
   // iiiiiiiiiiii defines RotatedImm8.
   constexpr IValueT Opcode = B3; // ie. 1000
   emitCompareOp(Opcode, OpRn, OpSrc1, Cond);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice