Fix ARM emit() methods to count instructions generated.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 66 matching lines @@
 
 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode,
                                    Type Ty) const {
   Str << Opcode << getPredicate() << "." << Ty;
 }
 
 CondARM32::Cond InstARM32::getOppositeCondition(CondARM32::Cond Cond) {
   return InstARM32CondAttributes[Cond].Opposite;
 }
 
+void InstARM32::startNextInst(const Cfg *Func) const {
+  if (auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>())
+    Asm->startNextInst();
+}
+
 void InstARM32::emitUsingTextFixup(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   GlobalContext *Ctx = Func->getContext();
   if (Ctx->getFlags().getDisableHybridAssembly()) {
     UnimplementedError(Ctx->getFlags());
     return;
   }
   ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   std::string Buffer;
   llvm::raw_string_ostream StrBuf(Buffer);
   OstreamLocker L(Ctx);
   Ostream &OldStr = Ctx->getStrEmit();
   Ctx->setStrEmit(StrBuf);
+  // Start counting instructions here, so that emit() methods don't
+  // need to call this for the first instruction.
+  Asm->startFirstInst();
   emit(Func);
   Ctx->setStrEmit(OldStr);
-  Asm->emitTextInst(StrBuf.str());
+  Asm->emitTextInst(StrBuf.str(),
+                    Asm->getNumberEmittedInsts() * sizeof(uint32_t));
 }
 
 void InstARM32::emitIAS(const Cfg *Func) const { emitUsingTextFixup(Func); }
 
 void InstARM32Pred::emitUnaryopGPR(const char *Opcode,
                                    const InstARM32Pred *Inst, const Cfg *Func,
                                    bool NeedsWidthSuffix) {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 1);
   Type SrcTy = Inst->getSrc(0)->getType();
@@ skipping 681 matching lines @@
   Str << "\t"
       << "b" << getPredicate() << "\t";
   if (Label) {
     Str << Label->getName(Func);
   } else {
     if (isUnconditionalBranch()) {
       Str << getTargetFalse()->getAsmName();
     } else {
       Str << getTargetTrue()->getAsmName();
       if (getTargetFalse()) {
+        startNextInst(Func);

[Jim Stichnoth, 2015/11/04 23:45:26]

This is interesting.  Are our ARM conditional branches really represented as a
compound instruction of a conditional branch to the "true" target followed by an
unconditional branch to the "false" target?  This may need to be changed to
enable branch optimizations.

         Str << "\n\t"
             << "b"
             << "\t" << getTargetFalse()->getAsmName();
       }
     }
   }
 }
 
 void InstARM32Br::emitIAS(const Cfg *Func) const {
   if (!Func->getContext()->getFlags().getAllowUnsafeIas())
@@ skipping 239 matching lines @@
         Op->emit(Func);
         PrintComma = true;
       }
     }
     Str << "}\n";
   }
 
   for (const Operand *Op : Dests) {
     if (isScalarIntegerType(Op->getType()))
       continue;
+    startNextInst(Func);
     Str << "\t"
         << "vpop"
         << "\t{";
     Op->emit(Func);
     Str << "}\n";
   }
 }
 
 void InstARM32Pop::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
@@ skipping 50 matching lines @@
     Operand *Op = getSrc(i - 1);
     if (isScalarIntegerType(Op->getType()))
       continue;
     Str << "\t"
         << "vpush"
         << "\t{";
     Op->emit(Func);
     Str << "}\n";
   }
   if (IntegerCount != 0) {
+    startNextInst(Func);
     Str << "\t"
         << "push"
         << "\t{";
     bool PrintComma = false;
     for (SizeT i = 0; i < getSrcSize(); ++i) {
       Operand *Op = getSrc(i);
       if (isScalarIntegerType(Op->getType())) {
         if (PrintComma)
           Str << ", ";
         Op->emit(Func);
@@ skipping 447 matching lines @@
 template class InstARM32UnaryopGPR<InstARM32::Rbit, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rev, false>;
 template class InstARM32UnaryopGPR<InstARM32::Sxt, true>;
 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
 
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace Ice