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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file | 3 // found in the LICENSE file |
4 | 4 |
5 #include "test/unittests/compiler/instruction-selector-unittest.h" | 5 #include "test/unittests/compiler/instruction-selector-unittest.h" |
6 | 6 |
7 namespace v8 { | 7 namespace v8 { |
8 namespace internal { | 8 namespace internal { |
9 namespace compiler { | 9 namespace compiler { |
10 | 10 |
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642 Stream s = m.Build(); | 642 Stream s = m.Build(); |
643 ASSERT_EQ(1U, s.size()); | 643 ASSERT_EQ(1U, s.size()); |
644 EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode()); | 644 EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode()); |
645 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); | 645 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); |
646 } | 646 } |
647 | 647 |
648 | 648 |
649 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { | 649 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { |
650 const MemoryAccess memacc = GetParam(); | 650 const MemoryAccess memacc = GetParam(); |
651 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); | 651 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); |
652 m.Store(memacc.type, m.Parameter(0), m.Parameter(1)); | 652 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); |
| 653 m.Store(store_rep, m.Parameter(0), m.Parameter(1)); |
653 m.Return(m.Int32Constant(0)); | 654 m.Return(m.Int32Constant(0)); |
654 Stream s = m.Build(); | 655 Stream s = m.Build(); |
655 ASSERT_EQ(1U, s.size()); | 656 ASSERT_EQ(1U, s.size()); |
656 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); | 657 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); |
657 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); | 658 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); |
658 } | 659 } |
659 | 660 |
660 INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, | 661 INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, |
661 InstructionSelectorMemoryAccessTest, | 662 InstructionSelectorMemoryAccessTest, |
662 ::testing::ValuesIn(kMemoryAccesses)); | 663 ::testing::ValuesIn(kMemoryAccesses)); |
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690 | 691 |
691 // ---------------------------------------------------------------------------- | 692 // ---------------------------------------------------------------------------- |
692 // Store immediate. | 693 // Store immediate. |
693 // ---------------------------------------------------------------------------- | 694 // ---------------------------------------------------------------------------- |
694 | 695 |
695 | 696 |
696 TEST_P(InstructionSelectorMemoryAccessImmTest, StoreWithImmediateIndex) { | 697 TEST_P(InstructionSelectorMemoryAccessImmTest, StoreWithImmediateIndex) { |
697 const MemoryAccessImm memacc = GetParam(); | 698 const MemoryAccessImm memacc = GetParam(); |
698 TRACED_FOREACH(int32_t, index, memacc.immediates) { | 699 TRACED_FOREACH(int32_t, index, memacc.immediates) { |
699 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); | 700 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); |
700 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), | 701 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); |
701 m.Parameter(1)); | 702 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1)); |
702 m.Return(m.Int32Constant(0)); | 703 m.Return(m.Int32Constant(0)); |
703 Stream s = m.Build(); | 704 Stream s = m.Build(); |
704 ASSERT_EQ(1U, s.size()); | 705 ASSERT_EQ(1U, s.size()); |
705 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); | 706 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); |
706 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); | 707 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); |
707 ASSERT_EQ(3U, s[0]->InputCount()); | 708 ASSERT_EQ(3U, s[0]->InputCount()); |
708 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); | 709 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); |
709 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); | 710 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); |
710 EXPECT_EQ(0U, s[0]->OutputCount()); | 711 EXPECT_EQ(0U, s[0]->OutputCount()); |
711 } | 712 } |
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739 EXPECT_EQ(2U, s[0]->InputCount()); | 740 EXPECT_EQ(2U, s[0]->InputCount()); |
740 EXPECT_EQ(1U, s[0]->OutputCount()); | 741 EXPECT_EQ(1U, s[0]->OutputCount()); |
741 } | 742 } |
742 } | 743 } |
743 | 744 |
744 TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest, | 745 TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest, |
745 StoreWithImmediateIndex) { | 746 StoreWithImmediateIndex) { |
746 const MemoryAccessImm1 memacc = GetParam(); | 747 const MemoryAccessImm1 memacc = GetParam(); |
747 TRACED_FOREACH(int32_t, index, memacc.immediates) { | 748 TRACED_FOREACH(int32_t, index, memacc.immediates) { |
748 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); | 749 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); |
749 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), | 750 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); |
750 m.Parameter(1)); | 751 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1)); |
751 m.Return(m.Int32Constant(0)); | 752 m.Return(m.Int32Constant(0)); |
752 Stream s = m.Build(); | 753 Stream s = m.Build(); |
753 ASSERT_EQ(2U, s.size()); | 754 ASSERT_EQ(2U, s.size()); |
754 // kMips64Add is expected opcode | 755 // kMips64Add is expected opcode |
755 // size more than 16 bits wide | 756 // size more than 16 bits wide |
756 EXPECT_EQ(kMips64Dadd, s[0]->arch_opcode()); | 757 EXPECT_EQ(kMips64Dadd, s[0]->arch_opcode()); |
757 EXPECT_EQ(kMode_None, s[0]->addressing_mode()); | 758 EXPECT_EQ(kMode_None, s[0]->addressing_mode()); |
758 EXPECT_EQ(2U, s[0]->InputCount()); | 759 EXPECT_EQ(2U, s[0]->InputCount()); |
759 EXPECT_EQ(1U, s[0]->OutputCount()); | 760 EXPECT_EQ(1U, s[0]->OutputCount()); |
760 } | 761 } |
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866 EXPECT_EQ(kMips64AbsD, s[0]->arch_opcode()); | 867 EXPECT_EQ(kMips64AbsD, s[0]->arch_opcode()); |
867 ASSERT_EQ(1U, s[0]->InputCount()); | 868 ASSERT_EQ(1U, s[0]->InputCount()); |
868 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); | 869 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
869 ASSERT_EQ(1U, s[0]->OutputCount()); | 870 ASSERT_EQ(1U, s[0]->OutputCount()); |
870 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); | 871 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
871 } | 872 } |
872 | 873 |
873 } // namespace compiler | 874 } // namespace compiler |
874 } // namespace internal | 875 } // namespace internal |
875 } // namespace v8 | 876 } // namespace v8 |
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