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Side by Side Diff: test/unittests/compiler/ia32/instruction-selector-ia32-unittest.cc

Issue 1425633002: [Interpreter] Add support for loading from / storing to outer context variables. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@int_conditional
Patch Set: Fix interpreter-assembler-unittests Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "test/unittests/compiler/instruction-selector-unittest.h" 5 #include "test/unittests/compiler/instruction-selector-unittest.h"
6 6
7 namespace v8 { 7 namespace v8 {
8 namespace internal { 8 namespace internal {
9 namespace compiler { 9 namespace compiler {
10 10
(...skipping 231 matching lines...) Expand 10 before | Expand all | Expand 10 after
242 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); 242 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
243 } 243 }
244 EXPECT_EQ(1U, s[0]->OutputCount()); 244 EXPECT_EQ(1U, s[0]->OutputCount());
245 } 245 }
246 } 246 }
247 247
248 248
249 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { 249 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
250 const MemoryAccess memacc = GetParam(); 250 const MemoryAccess memacc = GetParam();
251 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); 251 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type);
252 m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2)); 252 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier);
253 m.Store(store_rep, m.Parameter(0), m.Parameter(1), m.Parameter(2));
253 m.Return(m.Int32Constant(0)); 254 m.Return(m.Int32Constant(0));
254 Stream s = m.Build(); 255 Stream s = m.Build();
255 ASSERT_EQ(1U, s.size()); 256 ASSERT_EQ(1U, s.size());
256 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); 257 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
257 EXPECT_EQ(3U, s[0]->InputCount()); 258 EXPECT_EQ(3U, s[0]->InputCount());
258 EXPECT_EQ(0U, s[0]->OutputCount()); 259 EXPECT_EQ(0U, s[0]->OutputCount());
259 } 260 }
260 261
261 262
262 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateBase) { 263 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateBase) {
263 const MemoryAccess memacc = GetParam(); 264 const MemoryAccess memacc = GetParam();
264 TRACED_FOREACH(int32_t, base, kImmediates) { 265 TRACED_FOREACH(int32_t, base, kImmediates) {
265 StreamBuilder m(this, kMachInt32, kMachInt32, memacc.type); 266 StreamBuilder m(this, kMachInt32, kMachInt32, memacc.type);
266 m.Store(memacc.type, m.Int32Constant(base), m.Parameter(0), m.Parameter(1)); 267 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier);
268 m.Store(store_rep, m.Int32Constant(base), m.Parameter(0), m.Parameter(1));
267 m.Return(m.Int32Constant(0)); 269 m.Return(m.Int32Constant(0));
268 Stream s = m.Build(); 270 Stream s = m.Build();
269 ASSERT_EQ(1U, s.size()); 271 ASSERT_EQ(1U, s.size());
270 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); 272 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
271 if (base == 0) { 273 if (base == 0) {
272 ASSERT_EQ(2U, s[0]->InputCount()); 274 ASSERT_EQ(2U, s[0]->InputCount());
273 } else { 275 } else {
274 ASSERT_EQ(3U, s[0]->InputCount()); 276 ASSERT_EQ(3U, s[0]->InputCount());
275 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); 277 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
276 EXPECT_EQ(base, s.ToInt32(s[0]->InputAt(1))); 278 EXPECT_EQ(base, s.ToInt32(s[0]->InputAt(1)));
277 } 279 }
278 EXPECT_EQ(0U, s[0]->OutputCount()); 280 EXPECT_EQ(0U, s[0]->OutputCount());
279 } 281 }
280 } 282 }
281 283
282 284
283 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) { 285 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) {
284 const MemoryAccess memacc = GetParam(); 286 const MemoryAccess memacc = GetParam();
285 TRACED_FOREACH(int32_t, index, kImmediates) { 287 TRACED_FOREACH(int32_t, index, kImmediates) {
286 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); 288 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type);
287 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), 289 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier);
288 m.Parameter(1)); 290 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1));
289 m.Return(m.Int32Constant(0)); 291 m.Return(m.Int32Constant(0));
290 Stream s = m.Build(); 292 Stream s = m.Build();
291 ASSERT_EQ(1U, s.size()); 293 ASSERT_EQ(1U, s.size());
292 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); 294 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
293 if (index == 0) { 295 if (index == 0) {
294 ASSERT_EQ(2U, s[0]->InputCount()); 296 ASSERT_EQ(2U, s[0]->InputCount());
295 } else { 297 } else {
296 ASSERT_EQ(3U, s[0]->InputCount()); 298 ASSERT_EQ(3U, s[0]->InputCount());
297 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); 299 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
298 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); 300 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
(...skipping 13 matching lines...) Expand all
312 314
313 315
314 class AddressingModeUnitTest : public InstructionSelectorTest { 316 class AddressingModeUnitTest : public InstructionSelectorTest {
315 public: 317 public:
316 AddressingModeUnitTest() : m(NULL) { Reset(); } 318 AddressingModeUnitTest() : m(NULL) { Reset(); }
317 ~AddressingModeUnitTest() { delete m; } 319 ~AddressingModeUnitTest() { delete m; }
318 320
319 void Run(Node* base, Node* load_index, Node* store_index, 321 void Run(Node* base, Node* load_index, Node* store_index,
320 AddressingMode mode) { 322 AddressingMode mode) {
321 Node* load = m->Load(kMachInt32, base, load_index); 323 Node* load = m->Load(kMachInt32, base, load_index);
322 m->Store(kMachInt32, base, store_index, load); 324 m->Store(StoreRepresentation(kMachInt32, kNoWriteBarrier), base,
325 store_index, load);
323 m->Return(m->Int32Constant(0)); 326 m->Return(m->Int32Constant(0));
324 Stream s = m->Build(); 327 Stream s = m->Build();
325 ASSERT_EQ(2U, s.size()); 328 ASSERT_EQ(2U, s.size());
326 EXPECT_EQ(mode, s[0]->addressing_mode()); 329 EXPECT_EQ(mode, s[0]->addressing_mode());
327 EXPECT_EQ(mode, s[1]->addressing_mode()); 330 EXPECT_EQ(mode, s[1]->addressing_mode());
328 } 331 }
329 332
330 Node* zero; 333 Node* zero;
331 Node* null_ptr; 334 Node* null_ptr;
332 Node* non_zero; 335 Node* non_zero;
(...skipping 501 matching lines...) Expand 10 before | Expand all | Expand 10 after
834 EXPECT_EQ(kIA32Lzcnt, s[0]->arch_opcode()); 837 EXPECT_EQ(kIA32Lzcnt, s[0]->arch_opcode());
835 ASSERT_EQ(1U, s[0]->InputCount()); 838 ASSERT_EQ(1U, s[0]->InputCount());
836 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 839 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
837 ASSERT_EQ(1U, s[0]->OutputCount()); 840 ASSERT_EQ(1U, s[0]->OutputCount());
838 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 841 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
839 } 842 }
840 843
841 } // namespace compiler 844 } // namespace compiler
842 } // namespace internal 845 } // namespace internal
843 } // namespace v8 846 } // namespace v8
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