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Side by Side Diff: src/mips64/simulator-mips64.cc

Issue 1425003003: MIPS64: Fix missing DIVU,MODU,MULU,MUHU r6 instructions in simulator. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS64 10 #if V8_TARGET_ARCH_MIPS64
(...skipping 3375 matching lines...) Expand 10 before | Expand all | Expand 10 after
3386 default: 3386 default:
3387 UNIMPLEMENTED_MIPS(); 3387 UNIMPLEMENTED_MIPS();
3388 break; 3388 break;
3389 } 3389 }
3390 } 3390 }
3391 break; 3391 break;
3392 } 3392 }
3393 case MULTU: 3393 case MULTU:
3394 u64hilo = static_cast<uint64_t>(rs_u() & 0xffffffff) * 3394 u64hilo = static_cast<uint64_t>(rs_u() & 0xffffffff) *
3395 static_cast<uint64_t>(rt_u() & 0xffffffff); 3395 static_cast<uint64_t>(rt_u() & 0xffffffff);
3396 set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff)); 3396 if (kArchVariant != kMips64r6) {
3397 set_register(HI, static_cast<int32_t>(u64hilo >> 32)); 3397 set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff));
3398 set_register(HI, static_cast<int32_t>(u64hilo >> 32));
3399 } else {
3400 switch (sa()) {
3401 case MUL_OP:
3402 set_register(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff));
3403 break;
3404 case MUH_OP:
3405 set_register(rd_reg(), static_cast<int32_t>(u64hilo >> 32));
3406 break;
3407 default:
3408 UNIMPLEMENTED_MIPS();
3409 break;
3410 }
3411 }
3398 break; 3412 break;
3399 case DMULT: // DMULT == D_MUL_MUH. 3413 case DMULT: // DMULT == D_MUL_MUH.
3400 if (kArchVariant != kMips64r6) { 3414 if (kArchVariant != kMips64r6) {
3401 set_register(LO, rs() * rt()); 3415 set_register(LO, rs() * rt());
3402 set_register(HI, MultiplyHighSigned(rs(), rt())); 3416 set_register(HI, MultiplyHighSigned(rs(), rt()));
3403 } else { 3417 } else {
3404 switch (sa()) { 3418 switch (sa()) {
3405 case MUL_OP: 3419 case MUL_OP:
3406 set_register(rd_reg(), rs() * rt()); 3420 set_register(rd_reg(), rs() * rt());
3407 break; 3421 break;
(...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after
3455 UNIMPLEMENTED_MIPS(); 3469 UNIMPLEMENTED_MIPS();
3456 break; 3470 break;
3457 } 3471 }
3458 break; 3472 break;
3459 default: 3473 default:
3460 break; 3474 break;
3461 } 3475 }
3462 break; 3476 break;
3463 } 3477 }
3464 case DIVU: 3478 case DIVU:
3465 if (rt_u() != 0) { 3479 switch (kArchVariant) {
3466 uint32_t rt_u_32 = static_cast<uint32_t>(rt_u()); 3480 case kMips64r6: {
3467 uint32_t rs_u_32 = static_cast<uint32_t>(rs_u()); 3481 uint32_t rt_u_32 = static_cast<uint32_t>(rt_u());
3468 set_register(LO, rs_u_32 / rt_u_32); 3482 uint32_t rs_u_32 = static_cast<uint32_t>(rs_u());
3469 set_register(HI, rs_u_32 % rt_u_32); 3483 switch (get_instr()->SaValue()) {
3484 case DIV_OP:
3485 if (rt_u_32 != 0) {
3486 set_register(rd_reg(), rs_u_32 / rt_u_32);
3487 }
3488 break;
3489 case MOD_OP:
3490 if (rt_u() != 0) {
3491 set_register(rd_reg(), rs_u_32 % rt_u_32);
3492 }
3493 break;
3494 default:
3495 UNIMPLEMENTED_MIPS();
3496 break;
3497 }
3498 } break;
3499 default: {
3500 if (rt_u() != 0) {
3501 uint32_t rt_u_32 = static_cast<uint32_t>(rt_u());
3502 uint32_t rs_u_32 = static_cast<uint32_t>(rs_u());
3503 set_register(LO, rs_u_32 / rt_u_32);
3504 set_register(HI, rs_u_32 % rt_u_32);
3505 }
3506 }
3470 } 3507 }
3471 break; 3508 break;
3472 case DDIVU: 3509 case DDIVU:
3473 if (rt_u() != 0) { 3510 switch (kArchVariant) {
3474 set_register(LO, rs_u() / rt_u()); 3511 case kMips64r6: {
3475 set_register(HI, rs_u() % rt_u()); 3512 switch (get_instr()->SaValue()) {
3513 case DIV_OP:
3514 if (rt_u() != 0) {
3515 set_register(rd_reg(), rs_u() / rt_u());
3516 }
3517 break;
3518 case MOD_OP:
3519 if (rt_u() != 0) {
3520 set_register(rd_reg(), rs_u() % rt_u());
3521 }
3522 break;
3523 default:
3524 UNIMPLEMENTED_MIPS();
3525 break;
3526 }
3527 } break;
3528 default: {
3529 if (rt_u() != 0) {
3530 set_register(LO, rs_u() / rt_u());
3531 set_register(HI, rs_u() % rt_u());
3532 }
3533 }
3476 } 3534 }
3477 break; 3535 break;
3478 case ADD: 3536 case ADD:
3479 case DADD: 3537 case DADD:
3480 if (HaveSameSign(rs(), rt())) { 3538 if (HaveSameSign(rs(), rt())) {
3481 if (rs() > 0) { 3539 if (rs() > 0) {
3482 if (rs() > (Registers::kMaxValue - rt())) { 3540 if (rs() > (Registers::kMaxValue - rt())) {
3483 SignalException(kIntegerOverflow); 3541 SignalException(kIntegerOverflow);
3484 } 3542 }
3485 } else if (rs() < 0) { 3543 } else if (rs() < 0) {
(...skipping 1009 matching lines...) Expand 10 before | Expand all | Expand 10 after
4495 } 4553 }
4496 4554
4497 4555
4498 #undef UNSUPPORTED 4556 #undef UNSUPPORTED
4499 } // namespace internal 4557 } // namespace internal
4500 } // namespace v8 4558 } // namespace v8
4501 4559
4502 #endif // USE_SIMULATOR 4560 #endif // USE_SIMULATOR
4503 4561
4504 #endif // V8_TARGET_ARCH_MIPS64 4562 #endif // V8_TARGET_ARCH_MIPS64
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