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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file | 3 // found in the LICENSE file |
4 | 4 |
5 #include "test/unittests/compiler/instruction-selector-unittest.h" | 5 #include "test/unittests/compiler/instruction-selector-unittest.h" |
6 | 6 |
7 namespace v8 { | 7 namespace v8 { |
8 namespace internal { | 8 namespace internal { |
9 namespace compiler { | 9 namespace compiler { |
10 | 10 |
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642 Stream s = m.Build(); | 642 Stream s = m.Build(); |
643 ASSERT_EQ(1U, s.size()); | 643 ASSERT_EQ(1U, s.size()); |
644 EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode()); | 644 EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode()); |
645 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); | 645 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); |
646 } | 646 } |
647 | 647 |
648 | 648 |
649 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { | 649 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { |
650 const MemoryAccess memacc = GetParam(); | 650 const MemoryAccess memacc = GetParam(); |
651 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); | 651 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); |
652 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); | 652 m.Store(memacc.type, m.Parameter(0), m.Parameter(1), kNoWriteBarrier); |
653 m.Store(store_rep, m.Parameter(0), m.Parameter(1)); | |
654 m.Return(m.Int32Constant(0)); | 653 m.Return(m.Int32Constant(0)); |
655 Stream s = m.Build(); | 654 Stream s = m.Build(); |
656 ASSERT_EQ(1U, s.size()); | 655 ASSERT_EQ(1U, s.size()); |
657 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); | 656 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); |
658 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); | 657 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); |
659 } | 658 } |
660 | 659 |
661 INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, | 660 INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, |
662 InstructionSelectorMemoryAccessTest, | 661 InstructionSelectorMemoryAccessTest, |
663 ::testing::ValuesIn(kMemoryAccesses)); | 662 ::testing::ValuesIn(kMemoryAccesses)); |
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691 | 690 |
692 // ---------------------------------------------------------------------------- | 691 // ---------------------------------------------------------------------------- |
693 // Store immediate. | 692 // Store immediate. |
694 // ---------------------------------------------------------------------------- | 693 // ---------------------------------------------------------------------------- |
695 | 694 |
696 | 695 |
697 TEST_P(InstructionSelectorMemoryAccessImmTest, StoreWithImmediateIndex) { | 696 TEST_P(InstructionSelectorMemoryAccessImmTest, StoreWithImmediateIndex) { |
698 const MemoryAccessImm memacc = GetParam(); | 697 const MemoryAccessImm memacc = GetParam(); |
699 TRACED_FOREACH(int32_t, index, memacc.immediates) { | 698 TRACED_FOREACH(int32_t, index, memacc.immediates) { |
700 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); | 699 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); |
701 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); | 700 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1), |
702 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1)); | 701 kNoWriteBarrier); |
703 m.Return(m.Int32Constant(0)); | 702 m.Return(m.Int32Constant(0)); |
704 Stream s = m.Build(); | 703 Stream s = m.Build(); |
705 ASSERT_EQ(1U, s.size()); | 704 ASSERT_EQ(1U, s.size()); |
706 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); | 705 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); |
707 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); | 706 EXPECT_EQ(kMode_MRI, s[0]->addressing_mode()); |
708 ASSERT_EQ(3U, s[0]->InputCount()); | 707 ASSERT_EQ(3U, s[0]->InputCount()); |
709 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); | 708 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); |
710 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); | 709 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); |
711 EXPECT_EQ(0U, s[0]->OutputCount()); | 710 EXPECT_EQ(0U, s[0]->OutputCount()); |
712 } | 711 } |
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740 EXPECT_EQ(2U, s[0]->InputCount()); | 739 EXPECT_EQ(2U, s[0]->InputCount()); |
741 EXPECT_EQ(1U, s[0]->OutputCount()); | 740 EXPECT_EQ(1U, s[0]->OutputCount()); |
742 } | 741 } |
743 } | 742 } |
744 | 743 |
745 TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest, | 744 TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest, |
746 StoreWithImmediateIndex) { | 745 StoreWithImmediateIndex) { |
747 const MemoryAccessImm1 memacc = GetParam(); | 746 const MemoryAccessImm1 memacc = GetParam(); |
748 TRACED_FOREACH(int32_t, index, memacc.immediates) { | 747 TRACED_FOREACH(int32_t, index, memacc.immediates) { |
749 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); | 748 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); |
750 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); | 749 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1), |
751 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1)); | 750 kNoWriteBarrier); |
752 m.Return(m.Int32Constant(0)); | 751 m.Return(m.Int32Constant(0)); |
753 Stream s = m.Build(); | 752 Stream s = m.Build(); |
754 ASSERT_EQ(2U, s.size()); | 753 ASSERT_EQ(2U, s.size()); |
755 // kMips64Add is expected opcode | 754 // kMips64Add is expected opcode |
756 // size more than 16 bits wide | 755 // size more than 16 bits wide |
757 EXPECT_EQ(kMips64Dadd, s[0]->arch_opcode()); | 756 EXPECT_EQ(kMips64Dadd, s[0]->arch_opcode()); |
758 EXPECT_EQ(kMode_None, s[0]->addressing_mode()); | 757 EXPECT_EQ(kMode_None, s[0]->addressing_mode()); |
759 EXPECT_EQ(2U, s[0]->InputCount()); | 758 EXPECT_EQ(2U, s[0]->InputCount()); |
760 EXPECT_EQ(1U, s[0]->OutputCount()); | 759 EXPECT_EQ(1U, s[0]->OutputCount()); |
761 } | 760 } |
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867 EXPECT_EQ(kMips64AbsD, s[0]->arch_opcode()); | 866 EXPECT_EQ(kMips64AbsD, s[0]->arch_opcode()); |
868 ASSERT_EQ(1U, s[0]->InputCount()); | 867 ASSERT_EQ(1U, s[0]->InputCount()); |
869 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); | 868 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
870 ASSERT_EQ(1U, s[0]->OutputCount()); | 869 ASSERT_EQ(1U, s[0]->OutputCount()); |
871 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); | 870 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
872 } | 871 } |
873 | 872 |
874 } // namespace compiler | 873 } // namespace compiler |
875 } // namespace internal | 874 } // namespace internal |
876 } // namespace v8 | 875 } // namespace v8 |
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