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Side by Side Diff: test/unittests/compiler/ia32/instruction-selector-ia32-unittest.cc

Issue 1424983003: [turbofan] Cleanup RawMachineAssembler::Store interface. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Ports. Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "test/unittests/compiler/instruction-selector-unittest.h" 5 #include "test/unittests/compiler/instruction-selector-unittest.h"
6 6
7 namespace v8 { 7 namespace v8 {
8 namespace internal { 8 namespace internal {
9 namespace compiler { 9 namespace compiler {
10 10
(...skipping 231 matching lines...) Expand 10 before | Expand all | Expand 10 after
242 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); 242 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
243 } 243 }
244 EXPECT_EQ(1U, s[0]->OutputCount()); 244 EXPECT_EQ(1U, s[0]->OutputCount());
245 } 245 }
246 } 246 }
247 247
248 248
249 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { 249 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
250 const MemoryAccess memacc = GetParam(); 250 const MemoryAccess memacc = GetParam();
251 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); 251 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type);
252 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); 252 m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2),
253 m.Store(store_rep, m.Parameter(0), m.Parameter(1), m.Parameter(2)); 253 kNoWriteBarrier);
254 m.Return(m.Int32Constant(0)); 254 m.Return(m.Int32Constant(0));
255 Stream s = m.Build(); 255 Stream s = m.Build();
256 ASSERT_EQ(1U, s.size()); 256 ASSERT_EQ(1U, s.size());
257 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); 257 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
258 EXPECT_EQ(3U, s[0]->InputCount()); 258 EXPECT_EQ(3U, s[0]->InputCount());
259 EXPECT_EQ(0U, s[0]->OutputCount()); 259 EXPECT_EQ(0U, s[0]->OutputCount());
260 } 260 }
261 261
262 262
263 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateBase) { 263 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateBase) {
264 const MemoryAccess memacc = GetParam(); 264 const MemoryAccess memacc = GetParam();
265 TRACED_FOREACH(int32_t, base, kImmediates) { 265 TRACED_FOREACH(int32_t, base, kImmediates) {
266 StreamBuilder m(this, kMachInt32, kMachInt32, memacc.type); 266 StreamBuilder m(this, kMachInt32, kMachInt32, memacc.type);
267 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); 267 m.Store(memacc.type, m.Int32Constant(base), m.Parameter(0), m.Parameter(1),
268 m.Store(store_rep, m.Int32Constant(base), m.Parameter(0), m.Parameter(1)); 268 kNoWriteBarrier);
269 m.Return(m.Int32Constant(0)); 269 m.Return(m.Int32Constant(0));
270 Stream s = m.Build(); 270 Stream s = m.Build();
271 ASSERT_EQ(1U, s.size()); 271 ASSERT_EQ(1U, s.size());
272 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); 272 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
273 if (base == 0) { 273 if (base == 0) {
274 ASSERT_EQ(2U, s[0]->InputCount()); 274 ASSERT_EQ(2U, s[0]->InputCount());
275 } else { 275 } else {
276 ASSERT_EQ(3U, s[0]->InputCount()); 276 ASSERT_EQ(3U, s[0]->InputCount());
277 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); 277 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
278 EXPECT_EQ(base, s.ToInt32(s[0]->InputAt(1))); 278 EXPECT_EQ(base, s.ToInt32(s[0]->InputAt(1)));
279 } 279 }
280 EXPECT_EQ(0U, s[0]->OutputCount()); 280 EXPECT_EQ(0U, s[0]->OutputCount());
281 } 281 }
282 } 282 }
283 283
284 284
285 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) { 285 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) {
286 const MemoryAccess memacc = GetParam(); 286 const MemoryAccess memacc = GetParam();
287 TRACED_FOREACH(int32_t, index, kImmediates) { 287 TRACED_FOREACH(int32_t, index, kImmediates) {
288 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); 288 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type);
289 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); 289 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1),
290 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1)); 290 kNoWriteBarrier);
291 m.Return(m.Int32Constant(0)); 291 m.Return(m.Int32Constant(0));
292 Stream s = m.Build(); 292 Stream s = m.Build();
293 ASSERT_EQ(1U, s.size()); 293 ASSERT_EQ(1U, s.size());
294 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode()); 294 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
295 if (index == 0) { 295 if (index == 0) {
296 ASSERT_EQ(2U, s[0]->InputCount()); 296 ASSERT_EQ(2U, s[0]->InputCount());
297 } else { 297 } else {
298 ASSERT_EQ(3U, s[0]->InputCount()); 298 ASSERT_EQ(3U, s[0]->InputCount());
299 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); 299 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
300 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); 300 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
(...skipping 13 matching lines...) Expand all
314 314
315 315
316 class AddressingModeUnitTest : public InstructionSelectorTest { 316 class AddressingModeUnitTest : public InstructionSelectorTest {
317 public: 317 public:
318 AddressingModeUnitTest() : m(NULL) { Reset(); } 318 AddressingModeUnitTest() : m(NULL) { Reset(); }
319 ~AddressingModeUnitTest() { delete m; } 319 ~AddressingModeUnitTest() { delete m; }
320 320
321 void Run(Node* base, Node* load_index, Node* store_index, 321 void Run(Node* base, Node* load_index, Node* store_index,
322 AddressingMode mode) { 322 AddressingMode mode) {
323 Node* load = m->Load(kMachInt32, base, load_index); 323 Node* load = m->Load(kMachInt32, base, load_index);
324 m->Store(StoreRepresentation(kMachInt32, kNoWriteBarrier), base, 324 m->Store(kMachInt32, base, store_index, load, kNoWriteBarrier);
325 store_index, load);
326 m->Return(m->Int32Constant(0)); 325 m->Return(m->Int32Constant(0));
327 Stream s = m->Build(); 326 Stream s = m->Build();
328 ASSERT_EQ(2U, s.size()); 327 ASSERT_EQ(2U, s.size());
329 EXPECT_EQ(mode, s[0]->addressing_mode()); 328 EXPECT_EQ(mode, s[0]->addressing_mode());
330 EXPECT_EQ(mode, s[1]->addressing_mode()); 329 EXPECT_EQ(mode, s[1]->addressing_mode());
331 } 330 }
332 331
333 Node* zero; 332 Node* zero;
334 Node* null_ptr; 333 Node* null_ptr;
335 Node* non_zero; 334 Node* non_zero;
(...skipping 501 matching lines...) Expand 10 before | Expand all | Expand 10 after
837 EXPECT_EQ(kIA32Lzcnt, s[0]->arch_opcode()); 836 EXPECT_EQ(kIA32Lzcnt, s[0]->arch_opcode());
838 ASSERT_EQ(1U, s[0]->InputCount()); 837 ASSERT_EQ(1U, s[0]->InputCount());
839 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 838 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
840 ASSERT_EQ(1U, s[0]->OutputCount()); 839 ASSERT_EQ(1U, s[0]->OutputCount());
841 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 840 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
842 } 841 }
843 842
844 } // namespace compiler 843 } // namespace compiler
845 } // namespace internal 844 } // namespace internal
846 } // namespace v8 845 } // namespace v8
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