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Side by Side Diff: test/unittests/compiler/arm/instruction-selector-arm-unittest.cc

Issue 1424983003: [turbofan] Cleanup RawMachineAssembler::Store interface. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Ports. Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits> 5 #include <limits>
6 6
7 #include "test/unittests/compiler/instruction-selector-unittest.h" 7 #include "test/unittests/compiler/instruction-selector-unittest.h"
8 8
9 namespace v8 { 9 namespace v8 {
10 namespace internal { 10 namespace internal {
(...skipping 1302 matching lines...) Expand 10 before | Expand all | Expand 10 after
1313 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); 1313 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
1314 ASSERT_EQ(1U, s[0]->OutputCount()); 1314 ASSERT_EQ(1U, s[0]->OutputCount());
1315 EXPECT_TRUE((s.*memacc.val_predicate)(s[0]->Output())); 1315 EXPECT_TRUE((s.*memacc.val_predicate)(s[0]->Output()));
1316 } 1316 }
1317 } 1317 }
1318 1318
1319 1319
1320 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) { 1320 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
1321 const MemoryAccess memacc = GetParam(); 1321 const MemoryAccess memacc = GetParam();
1322 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type); 1322 StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type);
1323 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); 1323 m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2),
1324 m.Store(store_rep, m.Parameter(0), m.Parameter(1), m.Parameter(2)); 1324 kNoWriteBarrier);
1325 m.Return(m.Int32Constant(0)); 1325 m.Return(m.Int32Constant(0));
1326 Stream s = m.Build(); 1326 Stream s = m.Build();
1327 ASSERT_EQ(1U, s.size()); 1327 ASSERT_EQ(1U, s.size());
1328 EXPECT_EQ(memacc.str_opcode, s[0]->arch_opcode()); 1328 EXPECT_EQ(memacc.str_opcode, s[0]->arch_opcode());
1329 EXPECT_EQ(kMode_Offset_RR, s[0]->addressing_mode()); 1329 EXPECT_EQ(kMode_Offset_RR, s[0]->addressing_mode());
1330 EXPECT_EQ(3U, s[0]->InputCount()); 1330 EXPECT_EQ(3U, s[0]->InputCount());
1331 EXPECT_EQ(0U, s[0]->OutputCount()); 1331 EXPECT_EQ(0U, s[0]->OutputCount());
1332 } 1332 }
1333 1333
1334 1334
1335 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) { 1335 TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) {
1336 const MemoryAccess memacc = GetParam(); 1336 const MemoryAccess memacc = GetParam();
1337 TRACED_FOREACH(int32_t, index, memacc.immediates) { 1337 TRACED_FOREACH(int32_t, index, memacc.immediates) {
1338 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type); 1338 StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type);
1339 StoreRepresentation store_rep(memacc.type, kNoWriteBarrier); 1339 m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1),
1340 m.Store(store_rep, m.Parameter(0), m.Int32Constant(index), m.Parameter(1)); 1340 kNoWriteBarrier);
1341 m.Return(m.Int32Constant(0)); 1341 m.Return(m.Int32Constant(0));
1342 Stream s = m.Build(); 1342 Stream s = m.Build();
1343 ASSERT_EQ(1U, s.size()); 1343 ASSERT_EQ(1U, s.size());
1344 EXPECT_EQ(memacc.str_opcode, s[0]->arch_opcode()); 1344 EXPECT_EQ(memacc.str_opcode, s[0]->arch_opcode());
1345 EXPECT_EQ(kMode_Offset_RI, s[0]->addressing_mode()); 1345 EXPECT_EQ(kMode_Offset_RI, s[0]->addressing_mode());
1346 ASSERT_EQ(3U, s[0]->InputCount()); 1346 ASSERT_EQ(3U, s[0]->InputCount());
1347 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind()); 1347 ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
1348 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1))); 1348 EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
1349 EXPECT_EQ(0U, s[0]->OutputCount()); 1349 EXPECT_EQ(0U, s[0]->OutputCount());
1350 } 1350 }
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2780 EXPECT_EQ(kArmClz, s[0]->arch_opcode()); 2780 EXPECT_EQ(kArmClz, s[0]->arch_opcode());
2781 ASSERT_EQ(1U, s[0]->InputCount()); 2781 ASSERT_EQ(1U, s[0]->InputCount());
2782 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 2782 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
2783 ASSERT_EQ(1U, s[0]->OutputCount()); 2783 ASSERT_EQ(1U, s[0]->OutputCount());
2784 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 2784 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
2785 } 2785 }
2786 2786
2787 } // namespace compiler 2787 } // namespace compiler
2788 } // namespace internal 2788 } // namespace internal
2789 } // namespace v8 2789 } // namespace v8
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