Handle MOV (immediate) and MOVT to load ARM global addresses.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 20 matching lines @@
 
 // The following define individual bits.
 static constexpr IValueT B0 = 1;
 static constexpr IValueT B1 = 1 << 1;
 static constexpr IValueT B2 = 1 << 2;
 static constexpr IValueT B3 = 1 << 3;
 static constexpr IValueT B4 = 1 << 4;
 static constexpr IValueT B5 = 1 << 5;
 static constexpr IValueT B6 = 1 << 6;
 static constexpr IValueT B21 = 1 << 21;
+static constexpr IValueT B22 = 1 << 22;
 static constexpr IValueT B24 = 1 << 24;
+static constexpr IValueT B25 = 1 << 25;
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on ARM section A5.1.
 static constexpr IValueT L = 1 << 20; // load (or store)
 static constexpr IValueT W = 1 << 21; // writeback base register
                                       // (or leave unchanged)
 static constexpr IValueT B = 1 << 22; // unsigned byte (or word)
 static constexpr IValueT U = 1 << 23; // positive (or negative)
                                       // offset/index
 static constexpr IValueT P = 1 << 24; // offset/pre-indexed
@@ skipping 163 matching lines @@
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
 } // end of anonymous namespace
 
 namespace Ice {
 namespace ARM32 {
 
+size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
+                                  const Assembler &Asm) const {
+  static constexpr const size_t FixupSize = sizeof(IValueT);
+  if (!BuildDefs::dump())
+    return FixupSize;
+  Ostream &Str = Ctx->getStrEmit();
+  IValueT Inst = Asm.load<IValueT>(position());
+  Str << "\tmov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
+      << RegARM32::RegNames[(Inst >> kRdShift) & 0xF]
+      << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
+      << "16:" << symbol(Ctx) << "\t@ .word "
+      << llvm::format_hex_no_prefix(Inst, 8) << "\n";
+  return FixupSize;
+}
+
+MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
+                                                      const Constant *Value) {
+  MoveRelocatableFixup *F =
+      new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
+  F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
+                     : llvm::ELF::R_ARM_MOVT_ABS);
+  F->set_value(Value);
+  Buffer.installFixup(F);
+  return F;
+}
+
 void AssemblerARM32::bindCfgNodeLabel(const CfgNode *Node) {
   GlobalContext *Ctx = Node->getCfg()->getContext();
   if (BuildDefs::dump() && !Ctx->getFlags().getDisableHybridAssembly()) {
     // Generate label name so that branches can find it.
     constexpr SizeT InstSize = 0;
     emitTextInst(Node->getAsmName() + ":", InstSize);
   }
   SizeT NodeNumber = Node->getIndex();
   assert(!getPreliminary());
   Label *L = getOrCreateCfgNodeLabel(NodeNumber);
@@ skipping 275 matching lines @@
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Src;
   // TODO(kschimpf) Handle other forms of mov.
   if (decodeOperand(OpSrc, Src) != DecodedAsRotatedImm8)
     return setNeedsTextFixup();
   // MOV (immediate) - ARM section A8.8.102, encoding A1:
   //   mov{S}<c> <Rd>, #<RotatedImm8>
   //
-  // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd,
-  // and iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this
-  // assembler.
+  // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd, and
+  // iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this assembler.
   constexpr bool SetFlags = false;
   if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
     // Conditions of rule violated.
     return setNeedsTextFixup();
   constexpr IValueT Rn = 0;
   constexpr IValueT Mov = B3 | B2 | B0; // 1101.
   emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src);
 }
 
+void AssemblerARM32::movw(const Operand *OpRd, const Operand *OpSrc,
+                          CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc);
+  if (Src == nullptr)

[Karl, 2015/10/29 18:35:06]

Added fallback if not relocatable constant.

+    return setNeedsTextFixup();
+  // MOV (immediate) - ARM section A8.8.102, encoding A2:
+  //  movw<c> <Rd>, #<imm16>
+  //
+  // cccc00110000iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, and
+  // iiiiiiiiiiiiiiii=imm16.
+  if (!isConditionDefined(Cond))
+    // Conditions of rule violated.
+    return setNeedsTextFixup();
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  // Use 0 for the lower 16 bits of the relocatable, and add a fixup to
+  // install the correct bits.
+  constexpr bool IsMovW = true;
+  emitFixup(createMoveFixup(IsMovW, Src));
+  constexpr IValueT Imm16 = 0;
+  const IValueT Encoding = encodeCondition(Cond) << kConditionShift | B25 |
+                           B24 | ((Imm16 >> 12) << 16) | Rd << kRdShift |
+                           (Imm16 & 0xfff);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::movt(const Operand *OpRd, const Operand *OpSrc,
+                          CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc);
+  if (Src == nullptr)

[Karl, 2015/10/29 18:35:06]

Added fallback if not relocatable constant.

+    return setNeedsTextFixup();
+  // MOVT - ARM section A8.8.102, encoding A2:
+  //  movt<c> <Rd>, #<imm16>
+  //
+  // cccc00110100iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, and
+  // iiiiiiiiiiiiiiii=imm16.
+  if (!isConditionDefined(Cond))
+    // Conditions of rule violated.
+    return setNeedsTextFixup();
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  // Use 0 for the lower 16 bits of the relocatable, and add a fixup to
+  // install the correct bits.
+  constexpr bool IsMovW = false;
+  emitFixup(createMoveFixup(IsMovW, Src));
+  constexpr IValueT Imm16 = 0;
+  const IValueT Encoding = encodeCondition(Cond) << kConditionShift | B25 |
+                           B24 | B22 | ((Imm16 >> 12) << 16) | Rd << kRdShift |
+                           (Imm16 & 0xfff);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   constexpr IValueT Sbc = B2 | B1; // 0110
@@ skipping 109 matching lines @@
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice