Handle MOV (immediate) and MOVT to load ARM global addresses.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 20 matching lines @@
 
 // The following define individual bits.
 static constexpr IValueT B0 = 1;
 static constexpr IValueT B1 = 1 << 1;
 static constexpr IValueT B2 = 1 << 2;
 static constexpr IValueT B3 = 1 << 3;
 static constexpr IValueT B4 = 1 << 4;
 static constexpr IValueT B5 = 1 << 5;
 static constexpr IValueT B6 = 1 << 6;
 static constexpr IValueT B21 = 1 << 21;
+static constexpr IValueT B22 = 1 << 22;
 static constexpr IValueT B24 = 1 << 24;
+static constexpr IValueT B25 = 1 << 25;
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on ARM section A5.1.
 static constexpr IValueT L = 1 << 20; // load (or store)
 static constexpr IValueT W = 1 << 21; // writeback base register
                                       // (or leave unchanged)
 static constexpr IValueT B = 1 << 22; // unsigned byte (or word)
 static constexpr IValueT U = 1 << 23; // positive (or negative)
                                       // offset/index
 static constexpr IValueT P = 1 << 24; // offset/pre-indexed
@@ skipping 163 matching lines @@
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
 } // end of anonymous namespace
 
 namespace Ice {
 namespace ARM32 {
 
+size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
+                                  const Assembler &Asm) const {
+  static constexpr const size_t FixupSize = sizeof(IValueT);
+  if (!BuildDefs::dump())
+    return FixupSize;
+  Ostream &Str = Ctx->getStrEmit();
+  IValueT Inst = Asm.load<IValueT>(position());
+  Str << "\t";
+  if (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC)

[Jim Stichnoth, 2015/10/28 22:28:55]

What do you think of a long statement like
  Str << "\t" 
      << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "movw" : "movt")
      << "\t" << RegNames[..] << ...

[Karl, 2015/10/29 16:57:53]

Done.

+    Str << "movw";
+  else
+    Str << "movt";
+  Str << "\t" << RegARM32::RegNames[(Inst >> kRdShift) & 0xF] << ", #:";
+  if (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC)
+    Str << "lower";
+  else
+    Str << "upper";
+  Str << "16:" << symbol(Ctx) << "\t@ .word ";
+  IValueT HexMask = 0xF;
+  for (int HexDigit = 2 * FixupSize; HexDigit > 0; --HexDigit) {

[Jim Stichnoth, 2015/10/28 22:28:55]

Can you use llvm::format_hex_no_prefix() ?  This is used in IceOperand.h.

[Karl, 2015/10/29 16:57:53]

Done.

+    Str.write_hex((Inst >> 4 * (HexDigit - 1)) & HexMask);
+  }
+  Str << "\n";
+  return FixupSize;
+}
+
+MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
+                                                      const Constant *Value) {
+  MoveRelocatableFixup *F =
+      new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
+  F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
+                     : llvm::ELF::R_ARM_MOVT_ABS);
+  F->set_value(Value);
+  Buffer.installFixup(F);
+  return F;
+}
+
 void AssemblerARM32::bindCfgNodeLabel(const CfgNode *Node) {
   if (BuildDefs::dump() && !Ctx->getFlags().getDisableHybridAssembly()) {
     // Generate label name so that branches can find it.
     constexpr SizeT InstSize = 0;
     emitTextInst(Node->getAsmName() + ":", InstSize);
   }
   SizeT NodeNumber = Node->getIndex();
   assert(!getPreliminary());
   Label *L = getOrCreateCfgNodeLabel(NodeNumber);
   this->bind(L);
@@ skipping 286 matching lines @@
   // assembler.
   constexpr bool SetFlags = false;
   if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
     // Conditions of rule violated.
     return setNeedsTextFixup();
   constexpr IValueT Rn = 0;
   constexpr IValueT Mov = B3 | B2 | B0; // 1101.
   emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src);
 }
 
+void AssemblerARM32::movw(const Operand *OpRd, const Operand *OpSrc,
+                          CondARM32::Cond Cond) {
+  (void)Cond;

[Jim Stichnoth, 2015/10/28 22:28:55]

Remove this?

[Karl, 2015/10/29 16:57:53]

Done.

+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  if (auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc)) {
+    // MOV (immediate) - ARM section A8.8.102, encoding A2:
+    //  movw<c> <Rd>, #<imm16>
+    //
+    // cccc00110000iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
+    // and iiiiiiiiiiiiiiii=imm16.
+    if (!isConditionDefined(Cond))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+    // Use 0 for the lower 16 bits of the relocatable, and add a

[Jim Stichnoth, 2015/10/28 22:28:55]

reflow comment to 80-col

[Karl, 2015/10/29 16:57:53]

Done.

+    // fixup to install the correct bits.
+    constexpr bool IsMovW = true;
+    emitFixup(createMoveFixup(IsMovW, Src));
+    constexpr IValueT Imm16 = 0;
+    const IValueT Encoding = encodeCondition(Cond) << kConditionShift | B25 |
+                             B24 | ((Imm16 >> 12) << 16) | Rd << kRdShift |
+                             (Imm16 & 0xfff);
+    emitInst(Encoding);
+  }
+  setNeedsTextFixup();

[Jim Stichnoth, 2015/10/28 22:28:55]

This call is a little puzzling because I think it serves two purposes.  First,
if you get all the way through without any of the conditions firing, it means
the IAS failed and we should fall back to a text fixup.  Second, if we emit a
movw from a ConstantRelocatable, we still need a text fixup (because we don't
know how to do it any other way in textual asm).

If my understanding is right, I think it would be better to have two separate
calls to setNeedsTextFixup(), each with a comment describing why.  Eventually of
course the latter one will be removed because all the IAS will be implemented.

[Karl, 2015/10/29 16:57:53]

Hmm, this is a mistake. It shouldn't even be there. We generated the fixup
above, and it generates the corresponding text form. Removing.
Adding fixup to InstARM32Mov{w,t}::emitIAS to generate fixup if needed.

+}
+
+void AssemblerARM32::movt(const Operand *OpRd, const Operand *OpSrc,
+                          CondARM32::Cond Cond) {
+  (void)Cond;

[Jim Stichnoth, 2015/10/28 22:28:55]

remove?

[Karl, 2015/10/29 16:57:53]

Done.

+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  if (auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc)) {
+    // MOVT - ARM section A8.8.102, encoding A2:
+    //  movt<c> <Rd>, #<imm16>
+    //
+    // cccc00110100iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
+    // and iiiiiiiiiiiiiiii=imm16.
+    if (!isConditionDefined(Cond))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+    // Use 0 for the lower 16 bits of the relocatable, and add a
+    // fixup to install the correct bits.
+    constexpr bool IsMovW = false;
+    emitFixup(createMoveFixup(IsMovW, Src));
+    constexpr IValueT Imm16 = 0;
+    const IValueT Encoding = encodeCondition(Cond) << kConditionShift | B25 |
+                             B24 | B22 | ((Imm16 >> 12) << 16) |
+                             Rd << kRdShift | (Imm16 & 0xfff);
+    emitInst(Encoding);
+  }
+  setNeedsTextFixup();

[Karl, 2015/10/29 16:57:53]

Removed this also.

+}
+
 void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond) {
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Address;
   if (decodeAddress(OpAddress, Address) != DecodedAsImmRegOffset)
     return setNeedsTextFixup();
   // STR (immediate) - ARM section A8.8.204, encoding A1:
   //   str<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
@@ skipping 65 matching lines @@
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice