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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1424773002: Add ADC (immediate) instruction to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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117 bool fixupIsPCRel(FixupKind Kind) const override { 117 bool fixupIsPCRel(FixupKind Kind) const override {
118 (void)Kind; 118 (void)Kind;
119 // TODO(kschimpf) Decide if we need this. 119 // TODO(kschimpf) Decide if we need this.
120 return false; 120 return false;
121 } 121 }
122 122
123 void bind(Label *label); 123 void bind(Label *label);
124 124
125 // List of instructions implemented by integrated assembler. 125 // List of instructions implemented by integrated assembler.
126 126
127 void adc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
128 bool SetFlags, CondARM32::Cond Cond);
129
127 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 130 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
128 bool SetFlags, CondARM32::Cond Cond); 131 bool SetFlags, CondARM32::Cond Cond);
129 132
130 void b(Label *L, CondARM32::Cond Cond); 133 void b(Label *L, CondARM32::Cond Cond);
131 134
132 void bkpt(uint16_t Imm16); 135 void bkpt(uint16_t Imm16);
133 136
134 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); 137 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
135 138
136 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); 139 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
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181 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); 184 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
182 185
183 // Returns the offset encoded in the branch instruction Inst. 186 // Returns the offset encoded in the branch instruction Inst.
184 static IOffsetT decodeBranchOffset(IValueT Inst); 187 static IOffsetT decodeBranchOffset(IValueT Inst);
185 }; 188 };
186 189
187 } // end of namespace ARM32 190 } // end of namespace ARM32
188 } // end of namespace Ice 191 } // end of namespace Ice
189 192
190 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 193 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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