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Side by Side Diff: runtime/vm/assembler_mips.h

Issue 14246039: Implements features to run "Hello, world!" on simulated MIPS. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 8 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_MIPS_H_ 5 #ifndef VM_ASSEMBLER_MIPS_H_
6 #define VM_ASSEMBLER_MIPS_H_ 6 #define VM_ASSEMBLER_MIPS_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_mips.h directly; use assembler.h instead. 9 #error Do not include assembler_mips.h directly; use assembler.h instead.
10 #endif 10 #endif
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184 // Only the tags field of the object is initialized. 184 // Only the tags field of the object is initialized.
185 void TryAllocate(const Class& cls, 185 void TryAllocate(const Class& cls,
186 Label* failure, 186 Label* failure,
187 bool near_jump, 187 bool near_jump,
188 Register instance_reg) { 188 Register instance_reg) {
189 UNIMPLEMENTED(); 189 UNIMPLEMENTED();
190 } 190 }
191 191
192 // Debugging and bringup support. 192 // Debugging and bringup support.
193 void Stop(const char* message); 193 void Stop(const char* message);
194
195 // TODO(zra): TraceSimMsg enables printing of helpful messages when
196 // --trace_sim is given. Eventually these calls will be changed to Comment.
197 void TraceSimMsg(const char* message);
194 void Unimplemented(const char* message); 198 void Unimplemented(const char* message);
195 void Untested(const char* message); 199 void Untested(const char* message);
196 void Unreachable(const char* message); 200 void Unreachable(const char* message);
197 201
198 static void InitializeMemoryWithBreakpoints(uword data, int length); 202 static void InitializeMemoryWithBreakpoints(uword data, int length);
199 203
200 void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3); 204 void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
201 205
202 const Code::Comments& GetCodeComments() const; 206 const Code::Comments& GetCodeComments() const;
203 207
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675 LoadImmediate(TMP1, value); 679 LoadImmediate(TMP1, value);
676 addu(rd, rs, TMP1); 680 addu(rd, rs, TMP1);
677 } 681 }
678 } 682 }
679 683
680 void AddImmediate(Register rd, int32_t value) { 684 void AddImmediate(Register rd, int32_t value) {
681 AddImmediate(rd, rd, value); 685 AddImmediate(rd, rd, value);
682 } 686 }
683 687
684 void BranchEqual(Register rd, int32_t value, Label* l) { 688 void BranchEqual(Register rd, int32_t value, Label* l) {
685 LoadImmediate(TMP1, value); 689 ASSERT(rd != CMPRES);
686 beq(rd, TMP1, l); 690 LoadImmediate(CMPRES, value);
691 beq(rd, CMPRES, l);
687 } 692 }
688 693
689 void BranchEqual(Register rd, const Object& object, Label* l) { 694 void BranchEqual(Register rd, const Object& object, Label* l) {
690 LoadObject(TMP1, object); 695 ASSERT(rd != CMPRES);
691 beq(rd, TMP1, l); 696 LoadObject(CMPRES, object);
697 beq(rd, CMPRES, l);
692 } 698 }
693 699
694 void BranchNotEqual(Register rd, int32_t value, Label* l) { 700 void BranchNotEqual(Register rd, int32_t value, Label* l) {
695 LoadImmediate(TMP1, value); 701 ASSERT(rd != CMPRES);
696 bne(rd, TMP1, l); 702 LoadImmediate(CMPRES, value);
703 bne(rd, CMPRES, l);
697 } 704 }
698 705
699 void BranchNotEqual(Register rd, const Object& object, Label* l) { 706 void BranchNotEqual(Register rd, const Object& object, Label* l) {
700 LoadObject(TMP1, object); 707 ASSERT(rd != CMPRES);
701 bne(rd, TMP1, l); 708 LoadObject(CMPRES, object);
709 bne(rd, CMPRES, l);
702 } 710 }
703 711
704 void BranchGreater(Register rd, int32_t value, Label* l) { 712 void BranchGreater(Register rd, int32_t value, Label* l) {
705 if (Utils::IsInt(kImmBits, -value)) { 713 if (Utils::IsInt(kImmBits, -value)) {
706 addiu(TMP1, rd, Immediate(-value)); 714 addiu(CMPRES, rd, Immediate(-value));
707 bgtz(TMP1, l); 715 bgtz(CMPRES, l);
708 } else { 716 } else {
709 LoadImmediate(TMP1, value); 717 LoadImmediate(CMPRES, value);
710 subu(TMP1, rd, TMP1); 718 subu(CMPRES, rd, CMPRES);
711 bgtz(TMP1, l); 719 bgtz(CMPRES, l);
712 } 720 }
713 } 721 }
714 722
715 void BranchGreater(Register rd, Register rs, Label* l) { 723 void BranchGreater(Register rd, Register rs, Label* l) {
716 subu(TMP1, rd, rs); 724 subu(CMPRES, rd, rs);
717 bgtz(TMP1, l); 725 bgtz(CMPRES, l);
718 } 726 }
719 727
720 void BranchGreaterEqual(Register rd, int32_t value, Label* l) { 728 void BranchGreaterEqual(Register rd, int32_t value, Label* l) {
721 if (Utils::IsInt(kImmBits, -value)) { 729 if (Utils::IsInt(kImmBits, -value)) {
722 addiu(TMP1, rd, Immediate(-value)); 730 addiu(CMPRES, rd, Immediate(-value));
723 bgez(TMP1, l); 731 bgez(CMPRES, l);
724 } else { 732 } else {
725 LoadImmediate(TMP1, value); 733 LoadImmediate(CMPRES, value);
726 subu(TMP1, rd, TMP1); 734 subu(CMPRES, rd, CMPRES);
727 bgez(TMP1, l); 735 bgez(CMPRES, l);
728 } 736 }
729 } 737 }
730 738
731 void BranchGreaterEqual(Register rd, Register rs, Label* l) { 739 void BranchGreaterEqual(Register rd, Register rs, Label* l) {
732 subu(TMP1, rd, rs); 740 subu(CMPRES, rd, rs);
733 bgez(TMP1, l); 741 bgez(CMPRES, l);
734 } 742 }
735 743
736 void BranchLess(Register rd, int32_t value, Label* l) { 744 void BranchLess(Register rd, int32_t value, Label* l) {
737 if (Utils::IsInt(kImmBits, -value)) { 745 if (Utils::IsInt(kImmBits, -value)) {
738 addiu(TMP1, rd, Immediate(-value)); 746 addiu(CMPRES, rd, Immediate(-value));
739 bltz(TMP1, l); 747 bltz(CMPRES, l);
740 } else { 748 } else {
741 LoadImmediate(TMP1, value); 749 LoadImmediate(CMPRES, value);
742 subu(TMP1, rd, TMP1); 750 subu(CMPRES, rd, CMPRES);
743 bltz(TMP1, l); 751 bltz(CMPRES, l);
744 } 752 }
745 } 753 }
746 754
747 void BranchLess(Register rd, Register rs, Label* l) { 755 void BranchLess(Register rd, Register rs, Label* l) {
748 subu(TMP1, rd, rs); 756 subu(CMPRES, rd, rs);
749 bltz(TMP1, l); 757 bltz(CMPRES, l);
750 } 758 }
751 759
752 void BranchLessEqual(Register rd, int32_t value, Label* l) { 760 void BranchLessEqual(Register rd, int32_t value, Label* l) {
753 if (Utils::IsInt(kImmBits, -value)) { 761 if (Utils::IsInt(kImmBits, -value)) {
754 addiu(TMP1, rd, Immediate(-value)); 762 addiu(CMPRES, rd, Immediate(-value));
755 blez(TMP1, l); 763 blez(CMPRES, l);
756 } else { 764 } else {
757 LoadImmediate(TMP1, value); 765 LoadImmediate(CMPRES, value);
758 subu(TMP1, rd, TMP1); 766 subu(CMPRES, rd, CMPRES);
759 blez(TMP1, l); 767 blez(CMPRES, l);
760 } 768 }
761 } 769 }
762 770
763 void BranchLessEqual(Register rd, Register rs, Label* l) { 771 void BranchLessEqual(Register rd, Register rs, Label* l) {
764 subu(TMP1, rd, rs); 772 subu(CMPRES, rd, rs);
765 blez(TMP1, l); 773 blez(CMPRES, l);
766 } 774 }
767 775
768 void Push(Register rt) { 776 void Push(Register rt) {
769 addiu(SP, SP, Immediate(-kWordSize)); 777 addiu(SP, SP, Immediate(-kWordSize));
770 sw(rt, Address(SP)); 778 sw(rt, Address(SP));
771 } 779 }
772 780
773 void Pop(Register rt) { 781 void Pop(Register rt) {
774 lw(rt, Address(SP)); 782 lw(rt, Address(SP));
775 addiu(SP, SP, Immediate(kWordSize)); 783 addiu(SP, SP, Immediate(kWordSize));
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981 Register value, 989 Register value,
982 Label* no_update); 990 Label* no_update);
983 991
984 DISALLOW_ALLOCATION(); 992 DISALLOW_ALLOCATION();
985 DISALLOW_COPY_AND_ASSIGN(Assembler); 993 DISALLOW_COPY_AND_ASSIGN(Assembler);
986 }; 994 };
987 995
988 } // namespace dart 996 } // namespace dart
989 997
990 #endif // VM_ASSEMBLER_MIPS_H_ 998 #endif // VM_ASSEMBLER_MIPS_H_
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