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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1424333002: [turbofan] Added the RoundInt64ToFloat64 instruction to TurboFan. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@BufferedRawMachineAssemblerTester
Patch Set: Fixed the type of RoundInt64ToFloat64 Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 55 matching lines...) Expand 10 before | Expand all | Expand 10 after
66 V(Mips64MaxD) \ 66 V(Mips64MaxD) \
67 V(Mips64MinD) \ 67 V(Mips64MinD) \
68 V(Mips64Float64RoundDown) \ 68 V(Mips64Float64RoundDown) \
69 V(Mips64Float64RoundTruncate) \ 69 V(Mips64Float64RoundTruncate) \
70 V(Mips64Float64RoundUp) \ 70 V(Mips64Float64RoundUp) \
71 V(Mips64CvtSD) \ 71 V(Mips64CvtSD) \
72 V(Mips64CvtDS) \ 72 V(Mips64CvtDS) \
73 V(Mips64TruncWD) \ 73 V(Mips64TruncWD) \
74 V(Mips64TruncUwD) \ 74 V(Mips64TruncUwD) \
75 V(Mips64CvtDW) \ 75 V(Mips64CvtDW) \
76 V(Mips64CvtDL) \
76 V(Mips64CvtDUw) \ 77 V(Mips64CvtDUw) \
77 V(Mips64Lb) \ 78 V(Mips64Lb) \
78 V(Mips64Lbu) \ 79 V(Mips64Lbu) \
79 V(Mips64Sb) \ 80 V(Mips64Sb) \
80 V(Mips64Lh) \ 81 V(Mips64Lh) \
81 V(Mips64Lhu) \ 82 V(Mips64Lhu) \
82 V(Mips64Sh) \ 83 V(Mips64Sh) \
83 V(Mips64Ld) \ 84 V(Mips64Ld) \
84 V(Mips64Lw) \ 85 V(Mips64Lw) \
85 V(Mips64Sw) \ 86 V(Mips64Sw) \
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after
117 #define TARGET_ADDRESSING_MODE_LIST(V) \ 118 #define TARGET_ADDRESSING_MODE_LIST(V) \
118 V(MRI) /* [%r0 + K] */ \ 119 V(MRI) /* [%r0 + K] */ \
119 V(MRR) /* [%r0 + %r1] */ 120 V(MRR) /* [%r0 + %r1] */
120 121
121 122
122 } // namespace compiler 123 } // namespace compiler
123 } // namespace internal 124 } // namespace internal
124 } // namespace v8 125 } // namespace v8
125 126
126 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 127 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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