Add Sbc(register) and Sbc(immediate) to integrated ARM assembler.

tests_lit/assembler/arm32/sub.ll

Index: tests_lit/assembler/arm32/sub.ll
diff --git a/tests_lit/assembler/arm32/sub.ll b/tests_lit/assembler/arm32/sub.ll
index 52371f42ef5194ac26710c09c5be04278b1f9b5a..51db745a379560edf524abc6721d395619ffd124 100644
--- a/tests_lit/assembler/arm32/sub.ll
+++ b/tests_lit/assembler/arm32/sub.ll
@@ -1,4 +1,6 @@
-; Show that we know how to translate instruction sub.
+; Show that we know how to translate sub.
+
+; NOTE: We use -O2 to get rid of memory stores.
 
 ; REQUIRES: allow_dump
 
@@ -18,24 +20,31 @@
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
 
-define internal i32 @sub1FromR0(i32 %p) {
+define internal i32 @Sub1FromR0(i32 %p) {
   %v = sub i32 %p, 1
   ret i32 %v
 }
 
-; ASM-LABEL: sub1FromR0:
-; ASM:	sub	r0, r0, #1
-; ASM:	bx	lr
+; ASM-LABEL: Sub1FromR0:
+; ASM-NEXT:  .LSub1FromR0$__0:
+; ASM-NEXT:     sub     r0, r0, #1
+; ASM-NEXT:     bx      lr
 
-; DIS-LABEL:00000000 <sub1FromR0>:
-; DIS-NEXT:   0:	e2400001
+; DIS-LABEL:00000000 <Sub1FromR0>:
+; DIS-NEXT:   0:        e2400001
+; DIS-NEXT:   4:        e12fff1e
 
-; IASM-LABEL: sub1FromR0:
-; IASM:	     .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe2
+; IASM-LABEL: Sub1FromR0:
+; IASM-LABEL: .LSub1FromR0$__0:
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0xe2
 
+; IASM-NEXT:    .byte 0x1e
+; IASM-NEXT:    .byte 0xff
+; IASM-NEXT:    .byte 0x2f
+; IASM-NEXT:    .byte 0xe1
 
 define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
   %v = sub i32 %p1, %p2
@@ -43,15 +52,72 @@ define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
 }
 
 ; ASM-LABEL: Sub2Regs:
-; ASM:       sub r0, r0, r1
-; ASM-NEXT:  bx lr
+; ASM-NEXT:  .LSub2Regs$__0:
+; ASM-NEXT:     sub r0, r0, r1
+; ASM-NEXT:     bx lr
 
 ; DIS-LABEL:00000010 <Sub2Regs>:
-; DIS-NEXT:  10:	e0400001
+; DIS-NEXT:  10:        e0400001
+; DIS-NEXT:  14:        e12fff1e
 
 ; IASM-LABEL: Sub2Regs:
-; IASM:      .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe0
+; IASM-NEXT:  .LSub2Regs$__0:
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0xe0
+
+; IASM-NEXT:    .byte 0x1e
+; IASM-NEXT:    .byte 0xff
+; IASM-NEXT:    .byte 0x2f
+; IASM-NEXT:    .byte 0xe1
+
+define internal i64 @SubI64FromR0R1(i64 %p) {
+  %v = sub i64 %p, 1
+  ret i64 %v
+}
+
+; ASM-LABEL:SubI64FromR0R1:
+; ASM-NEXT:.LSubI64FromR0R1$__0:
+; ASM-NEXT:     subs    r0, r0, #1
+; ASM-NEXT:     sbc     r1, r1, #0
+
+; DIS-LABEL:00000020 <SubI64FromR0R1>:
+; DIS-NEXT:  20:        e2500001
+; DIS-NEXT:  24:        e2c11000
+
+; IASM-LABEL:SubI64FromR0R1:
+; IASM-NEXT:.LSubI64FromR0R1$__0:
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x50
+; IASM-NEXT:    .byte 0xe2
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0xc1
+; IASM-NEXT:    .byte 0xe2
+
+define internal i64 @SubI64Regs(i64 %p1, i64 %p2) {
+  %v = sub i64 %p1, %p2
+  ret i64 %v
+}
+
+; ASM-LABEL:SubI64Regs:
+; ASM-NEXT:.LSubI64Regs$__0:
+; ASM-NEXT:     subs    r0, r0, r2
+; ASM-NEXT:     sbc     r1, r1, r3
+
+; DIS-LABEL:00000030 <SubI64Regs>:
+; DIS-NEXT:  30:	e0500002
+; DIS-NEXT:  34:	e0c11003
 
+; IASM-LABEL:SubI64Regs:
+; IASM-NEXT:.LSubI64Regs$__0:
+; IASM-NEXT:    .byte 0x2
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x50
+; IASM-NEXT:    .byte 0xe0
+; IASM-NEXT:    .byte 0x3
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0xc1
+; IASM-NEXT:    .byte 0xe0