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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1424213003: Add Sbc(register) and Sbc(immediate) to integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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132 void b(Label *L, CondARM32::Cond Cond); 132 void b(Label *L, CondARM32::Cond Cond);
133 133
134 void bkpt(uint16_t Imm16); 134 void bkpt(uint16_t Imm16);
135 135
136 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); 136 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
137 137
138 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); 138 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
139 139
140 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); 140 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
141 141
142 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
143 bool SetFlags, CondARM32::Cond Cond);
144
142 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); 145 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
143 146
144 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 147 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
145 bool SetFlags, CondARM32::Cond Cond); 148 bool SetFlags, CondARM32::Cond Cond);
146 149
147 static bool classof(const Assembler *Asm) { 150 static bool classof(const Assembler *Asm) {
148 return Asm->getKind() == Asm_ARM32; 151 return Asm->getKind() == Asm_ARM32;
149 } 152 }
150 153
151 void emitTextInst(const std::string &Text, SizeT InstSize = sizeof(IValueT)); 154 void emitTextInst(const std::string &Text, SizeT InstSize = sizeof(IValueT));
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183 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); 186 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
184 187
185 // Returns the offset encoded in the branch instruction Inst. 188 // Returns the offset encoded in the branch instruction Inst.
186 static IOffsetT decodeBranchOffset(IValueT Inst); 189 static IOffsetT decodeBranchOffset(IValueT Inst);
187 }; 190 };
188 191
189 } // end of namespace ARM32 192 } // end of namespace ARM32
190 } // end of namespace Ice 193 } // end of namespace Ice
191 194
192 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 195 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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