Subzero. ARM32. Address mode formation.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 526 matching lines @@
     Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred));
   }
   void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
   }
 
   /// Run a pass through stack variables and ensure that the offsets are legal.
   /// If the offset is not legal, use a new base register that accounts for the
   /// offset, such that the addressing mode offset bits are now legal.
   void legalizeStackSlots();
-  /// Returns true if the given Offset can be represented in a stack ldr/str.
-  bool isLegalVariableStackOffset(Type Ty, int32_t Offset) const;
-  /// Assuming Var needs its offset legalized, define a new base register
-  /// centered on the given Var's offset plus StackAdjust, and use it.
-  StackVariable *legalizeVariableSlot(Variable *Var, int32_t StackAdjust,
-                                      Variable *OrigBaseReg);
+  /// Returns true if the given Offset can be represented in a ldr/str.
+  bool isLegalMemOffset(Type Ty, int32_t Offset) const;
+  // Creates a new Base register centered around
+  // [OrigBaseReg, +/- Offset+StackAdjust].
+  Variable *newBaseRegister(int32_t Offset, int32_t StackAdjust,
+                            Variable *OrigBaseReg);
+  /// Creates a new, legal StackVariable w.r.t. ARM's Immediate requirements.
+  /// This method is not very smart: it will always create and return a new
+  /// StackVariable, even if Offset + StackAdjust is encodable.
+  StackVariable *legalizeStackSlot(Type Ty, int32_t Offset, int32_t StackAdjust,
+                                   Variable *OrigBaseReg, Variable **NewBaseReg,
+                                   int32_t *NewBaseOffset);
+  /// Legalizes Mov if its Source (or Destination) contains an invalid
+  /// immediate.
+  void legalizeMovStackAddrImm(InstARM32Mov *Mov, int32_t StackAdjust,
+                               Variable *OrigBaseReg, Variable **NewBaseReg,
+                               int32_t *NewBaseOffset);
 
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM];
   static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   static llvm::SmallBitVector ScratchRegs;
@@ skipping 44 matching lines @@
   private:
     uint32_t NumGPRRegsUsed = 0;
     llvm::SmallBitVector VFPRegsFree;
     llvm::SmallBitVector ValidF64Regs;
     llvm::SmallBitVector ValidV128Regs;
   };
 
 private:
   ~TargetARM32() override = default;
 
+  OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
+                                      Operand *Base);
+
   void lowerTruncToFlags(Operand *Src, CondARM32::Cond *CondIfTrue,
                          CondARM32::Cond *CondIfFalse);
+
   class BoolComputationTracker {
   public:
     BoolComputationTracker() = default;
     ~BoolComputationTracker() = default;
 
     void forgetProducers() { KnownComputations.clear(); }
     void recordProducers(CfgNode *Node);
 
     const Inst *getProducerOf(const Operand *Opnd) const {
       auto *Var = llvm::dyn_cast<Variable>(Opnd);
@@ skipping 83 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H