Subzero. ARM32. Address mode formation.

src/IceInstARM32.def

 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of ARM32 instructions in the form of x-macros.
@@ skipping 271 matching lines @@
   X(Reg_DREG_Last, = Reg_d31)                                                  \
   X(Reg_QREG_First, = Reg_q0)                                                  \
   X(Reg_QREG_Last, = Reg_q15)
 // define X(val, init)
 
 // Load/Store instruction width suffixes and FP/Vector element size suffixes
 // the # of offset bits allowed as part of an addressing mode (for sign or zero
 // extending load/stores).
 #define ICETYPEARM32_TABLE                                                     \
   /* tag,          element type, int_width, vec_width, addr bits sext, zext,   \
-     reg-reg addr allowed */                                                   \
-  X(IceType_void,  IceType_void, "" , ""    , 0 , 0 , 0)                       \
-  X(IceType_i1,    IceType_void, "b", ""    , 8 , 12, 1)                       \
-  X(IceType_i8,    IceType_void, "b", ""    , 8 , 12, 1)                       \
-  X(IceType_i16,   IceType_void, "h", ""    , 8 , 8 , 1)                       \
-  X(IceType_i32,   IceType_void, "" , ""    , 12, 12, 1)                       \
-  X(IceType_i64,   IceType_void, "d", ""    , 0 , 0 , 0)                       \
-  X(IceType_f32,   IceType_void, "" , ".f32", 8,  8 , 0)                       \
-  X(IceType_f64,   IceType_void, "" , ".f64", 8,  8 , 0)                       \
-  X(IceType_v4i1,  IceType_i32 , "" , ".i32", 0 , 0 , 1)                       \
-  X(IceType_v8i1,  IceType_i16 , "" , ".i16", 0 , 0 , 1)                       \
-  X(IceType_v16i1, IceType_i8  , "" , ".i8" , 0 , 0 , 1)                       \
-  X(IceType_v16i8, IceType_i8  , "" , ".i8" , 0 , 0 , 1)                       \
-  X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1)                       \
-  X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1)                       \
-  X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1)
-//#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr)
+     reg-reg addr allowed, shift allowed, */                                   \
+  X(IceType_void,  IceType_void, "" , ""    , 0 , 0 , 0, 0)                    \
+  X(IceType_i1,    IceType_void, "b", ""    , 8 , 12, 1, 1)                    \
+  X(IceType_i8,    IceType_void, "b", ""    , 8 , 12, 1, 1)                    \
+  X(IceType_i16,   IceType_void, "h", ""    , 8 , 8 , 1, 0)                    \
+  X(IceType_i32,   IceType_void, "" , ""    , 12, 12, 1, 1)                    \
+  X(IceType_i64,   IceType_void, "d", ""    , 12, 12, 1, 1)                    \
+  X(IceType_f32,   IceType_void, "" , ".f32", 8,  8 , 0, 0)                    \
+  X(IceType_f64,   IceType_void, "" , ".f64", 8,  8 , 0, 0)                    \
+  X(IceType_v4i1,  IceType_i32 , "" , ".i32", 0 , 0 , 1, 0)                    \
+  X(IceType_v8i1,  IceType_i16 , "" , ".i16", 0 , 0 , 1, 0)                    \
+  X(IceType_v16i1, IceType_i8  , "" , ".i8" , 0 , 0 , 1, 0)                    \
+  X(IceType_v16i8, IceType_i8  , "" , ".i8" , 0 , 0 , 1, 0)                    \
+  X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0)                    \
+  X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0)                    \
+  X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1, 0)
+//#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)
 
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 #define ICEINSTARM32SHIFT_TABLE                                                \
   /* enum value, emit */                                                       \
   X(LSL, "lsl")                                                                \
   X(LSR, "lsr")                                                                \
   X(ASR, "asr")                                                                \
   X(ROR, "ror")                                                                \
   X(RRX, "rrx")
 //#define X(tag, emit)
@@ skipping 15 matching lines @@
   X(LS, 9, HI, "ls")        /* unsigned lower or same */                       \
   X(GE, 10, LT, "ge")       /* signed greater than or equal */                 \
   X(LT, 11, GE, "lt")       /* signed less than */                             \
   X(GT, 12, LE, "gt")       /* signed greater than */                          \
   X(LE, 13, GT, "le")       /* signed less than or equal */                    \
   X(AL, 14, kNone, "")      /* always (unconditional) */                       \
   X(kNone, 15, kNone, "??") /* special condition / none */
 //#define X(tag, encode, opp, emit)
 
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF