Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(4)

Unified Diff: src/IceAssemblerARM32.cpp

Issue 1422253003: Add UMULL to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 1 month ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « src/IceAssemblerARM32.h ('k') | src/IceCfg.cpp » ('j') | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 338022fb32f954475fdc8182511964b5cc49e701..2b6f9e0de05fd7842d663948274ad9b9b8bc7dab 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -48,6 +48,7 @@ static constexpr IValueT B15 = 1 << 15;
static constexpr IValueT B20 = 1 << 20;
static constexpr IValueT B21 = 1 << 21;
static constexpr IValueT B22 = 1 << 22;
+static constexpr IValueT B23 = 1 << 23;
static constexpr IValueT B24 = 1 << 24;
static constexpr IValueT B25 = 1 << 25;
static constexpr IValueT B26 = 1 << 26;
@@ -1048,5 +1049,30 @@ void AssemblerARM32::tst(const Operand *OpRn, const Operand *OpSrc1,
emitCompareOp(Opcode, OpRn, OpSrc1, Cond);
}
+void AssemblerARM32::umull(const Operand *OpRdLo, const Operand *OpRdHi,
Jim Stichnoth 2015/11/06 22:26:42 Is this a situation where you would comment out um
Karl 2015/11/09 20:16:37 Yes. I forgot that. Commenting appropriate entries
+ const Operand *OpRn, const Operand *OpRm,
+ CondARM32::Cond Cond) {
+ // UMULL - ARM section A8.8.257, encoding A1:
+ // umull<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ //
+ // cccc0000100shhhhllllmmmm1001nnnn where hhhh=RdHi, llll=RdLo, nnnn=Rn,
+ // mmmm=Rm, and s=SetFlags
+ IValueT RdLo;
+ IValueT RdHi;
+ IValueT Rn;
+ IValueT Rm;
+ if (decodeOperand(OpRdLo, RdLo) != DecodedAsRegister ||
+ decodeOperand(OpRdHi, RdHi) != DecodedAsRegister ||
+ decodeOperand(OpRn, Rn) != DecodedAsRegister ||
+ decodeOperand(OpRm, Rm) != DecodedAsRegister)
+ return setNeedsTextFixup();
+ if (RdHi == RegARM32::Encoded_Reg_pc || RdLo == RegARM32::Encoded_Reg_pc ||
+ Rn == RegARM32::Encoded_Reg_pc || Rm == RegARM32::Encoded_Reg_pc ||
+ RdHi == RdLo)
+ llvm::report_fatal_error("Sdiv instruction unpredictable on pc");
Jim Stichnoth 2015/11/06 22:26:42 sdiv?
Karl 2015/11/09 20:16:37 Need to improve my cut/paste skills! Fixing.
+ constexpr bool SetFlags = false;
+ emitMulOp(Cond, B23, RdLo, RdHi, Rn, Rm, SetFlags);
+}
+
} // end of namespace ARM32
} // end of namespace Ice
« no previous file with comments | « src/IceAssemblerARM32.h ('k') | src/IceCfg.cpp » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698