Add UMULL to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 30 matching lines @@
 static constexpr IValueT B5 = 1 << 5;
 static constexpr IValueT B6 = 1 << 6;
 static constexpr IValueT B7 = 1 << 7;
 static constexpr IValueT B12 = 1 << 12;
 static constexpr IValueT B13 = 1 << 13;
 static constexpr IValueT B14 = 1 << 14;
 static constexpr IValueT B15 = 1 << 15;
 static constexpr IValueT B20 = 1 << 20;
 static constexpr IValueT B21 = 1 << 21;
 static constexpr IValueT B22 = 1 << 22;
+static constexpr IValueT B23 = 1 << 23;
 static constexpr IValueT B24 = 1 << 24;
 static constexpr IValueT B25 = 1 << 25;
 static constexpr IValueT B26 = 1 << 26;
 static constexpr IValueT B27 = 1 << 27;
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on ARM section A5.1.
 static constexpr IValueT L = 1 << 20; // load (or store)
 static constexpr IValueT W = 1 << 21; // writeback base register
                                       // (or leave unchanged)
@@ skipping 936 matching lines @@
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
   if (decodeOperand(OpSrc1, Rm) != DecodedAsRegister)
     return setNeedsTextFixup();
   if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
       Rm == RegARM32::Encoded_Reg_pc)
-    llvm::report_fatal_error("Sdiv instruction unpredictable on pc");
+    llvm::report_fatal_error("Udiv instruction unpredictable on pc");
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT Opcode = B21;
   emitDivOp(Cond, Opcode, Rd, Rn, Rm);
 }
 
 void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SUB (register) - ARM section A8.8.223, encoding A1:
   //   sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
@@ skipping 24 matching lines @@
   //
   // TST (immediate) - ARM section A8.8.240, encoding A1:
   //   tst<c> <Rn>, #<RotatedImm8>
   //
   // cccc00110001nnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, and
   // iiiiiiiiiiii defines RotatedImm8.
   constexpr IValueT Opcode = B3; // ie. 1000
   emitCompareOp(Opcode, OpRn, OpSrc1, Cond);
 }
 
+void AssemblerARM32::umull(const Operand *OpRdLo, const Operand *OpRdHi,
+                           const Operand *OpRn, const Operand *OpRm,
+                           CondARM32::Cond Cond) {
+  // UMULL - ARM section A8.8.257, encoding A1:
+  //   umull<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+  //
+  // cccc0000100shhhhllllmmmm1001nnnn where hhhh=RdHi, llll=RdLo, nnnn=Rn,
+  // mmmm=Rm, and s=SetFlags
+  IValueT RdLo;
+  IValueT RdHi;
+  IValueT Rn;
+  IValueT Rm;
+  if (decodeOperand(OpRdLo, RdLo) != DecodedAsRegister ||
+      decodeOperand(OpRdHi, RdHi) != DecodedAsRegister ||
+      decodeOperand(OpRn, Rn) != DecodedAsRegister ||
+      decodeOperand(OpRm, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  if (RdHi == RegARM32::Encoded_Reg_pc || RdLo == RegARM32::Encoded_Reg_pc ||
+      Rn == RegARM32::Encoded_Reg_pc || Rm == RegARM32::Encoded_Reg_pc ||
+      RdHi == RdLo)
+    llvm::report_fatal_error("Umull instruction unpredictable on pc");
+  constexpr bool SetFlags = false;
+  emitMulOp(Cond, B23, RdLo, RdHi, Rn, Rm, SetFlags);
+}
+
 } // end of namespace ARM32
 } // end of namespace Ice