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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #if V8_TARGET_ARCH_X64 | 5 #if V8_TARGET_ARCH_X64 |
6 | 6 |
7 #include "src/base/bits.h" | 7 #include "src/base/bits.h" |
8 #include "src/base/division-by-constant.h" | 8 #include "src/base/division-by-constant.h" |
9 #include "src/bootstrapper.h" | 9 #include "src/bootstrapper.h" |
10 #include "src/codegen.h" | 10 #include "src/codegen.h" |
(...skipping 3171 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3182 } | 3182 } |
3183 Label not_zero_src; | 3183 Label not_zero_src; |
3184 bsrq(dst, src); | 3184 bsrq(dst, src); |
3185 j(not_zero, ¬_zero_src, Label::kNear); | 3185 j(not_zero, ¬_zero_src, Label::kNear); |
3186 Set(dst, 127); // 127^63 == 64 | 3186 Set(dst, 127); // 127^63 == 64 |
3187 bind(¬_zero_src); | 3187 bind(¬_zero_src); |
3188 xorl(dst, Immediate(63)); // for x in [0..63], 63^x == 63 - x | 3188 xorl(dst, Immediate(63)); // for x in [0..63], 63^x == 63 - x |
3189 } | 3189 } |
3190 | 3190 |
3191 | 3191 |
| 3192 void MacroAssembler::Tzcntq(Register dst, Register src) { |
| 3193 if (CpuFeatures::IsSupported(BMI1)) { |
| 3194 CpuFeatureScope scope(this, BMI1); |
| 3195 tzcntq(dst, src); |
| 3196 return; |
| 3197 } |
| 3198 Label not_zero_src; |
| 3199 bsfq(dst, src); |
| 3200 j(not_zero, ¬_zero_src, Label::kNear); |
| 3201 // Define the result of tzcnt(0) separately, because bsf(0) is undefined. |
| 3202 Set(dst, 64); |
| 3203 bind(¬_zero_src); |
| 3204 } |
| 3205 |
| 3206 |
| 3207 void MacroAssembler::Tzcntq(Register dst, const Operand& src) { |
| 3208 if (CpuFeatures::IsSupported(BMI1)) { |
| 3209 CpuFeatureScope scope(this, BMI1); |
| 3210 tzcntq(dst, src); |
| 3211 return; |
| 3212 } |
| 3213 Label not_zero_src; |
| 3214 bsfq(dst, src); |
| 3215 j(not_zero, ¬_zero_src, Label::kNear); |
| 3216 // Define the result of tzcnt(0) separately, because bsf(0) is undefined. |
| 3217 Set(dst, 64); |
| 3218 bind(¬_zero_src); |
| 3219 } |
| 3220 |
| 3221 |
3192 void MacroAssembler::Tzcntl(Register dst, Register src) { | 3222 void MacroAssembler::Tzcntl(Register dst, Register src) { |
3193 if (CpuFeatures::IsSupported(BMI1)) { | 3223 if (CpuFeatures::IsSupported(BMI1)) { |
3194 CpuFeatureScope scope(this, BMI1); | 3224 CpuFeatureScope scope(this, BMI1); |
3195 tzcntl(dst, src); | 3225 tzcntl(dst, src); |
3196 return; | 3226 return; |
3197 } | 3227 } |
3198 Label not_zero_src; | 3228 Label not_zero_src; |
3199 bsfl(dst, src); | 3229 bsfl(dst, src); |
3200 j(not_zero, ¬_zero_src, Label::kNear); | 3230 j(not_zero, ¬_zero_src, Label::kNear); |
3201 Set(dst, 32); // The result of tzcnt is 32 if src = 0. | 3231 Set(dst, 32); // The result of tzcnt is 32 if src = 0. |
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5402 movl(rax, dividend); | 5432 movl(rax, dividend); |
5403 shrl(rax, Immediate(31)); | 5433 shrl(rax, Immediate(31)); |
5404 addl(rdx, rax); | 5434 addl(rdx, rax); |
5405 } | 5435 } |
5406 | 5436 |
5407 | 5437 |
5408 } // namespace internal | 5438 } // namespace internal |
5409 } // namespace v8 | 5439 } // namespace v8 |
5410 | 5440 |
5411 #endif // V8_TARGET_ARCH_X64 | 5441 #endif // V8_TARGET_ARCH_X64 |
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