arm64: clang assembler compatability

dl/sp/src/arm/arm64/armSP_FFT_CToC_FC32_Radix4_s.S

 //
 //  Copyright (c) 2013 The WebRTC project authors. All Rights Reserved.
 //
 //  Use of this source code is governed by a BSD-style license
 //  that can be found in the LICENSE file in the root of the source
 //  tree. An additional intellectual property rights grant can be found
 //  in the file PATENTS.  All contributing project authors may
 //  be found in the AUTHORS file in the root of the source tree.
 //
 //
@@ skipping 62 matching lines @@
 #define stepTwiddle     x10
 #define setCount        x11
 #define srcStep         x12
 #define setStep         x13
 #define dstStep         x14
 #define twStep          x15
 
 // Neon Registers
 
 #define dW1     v0.2s
+#define dW1s    v0.s
 #define dW2     v1.2s
+#define dW2s    v1.s
 #define dW3     v2.2s
+#define dW3s    v2.s
 
 #define dXr0    v4.2s
 #define dXi0    v5.2s
 #define dXr1    v6.2s
 #define dXi1    v7.2s
 #define dXr2    v8.2s
 #define dXi2    v9.2s
 #define dXr3    v10.2s
 #define dXi3    v11.2s
 #define dYr0    v12.2s
@@ skipping 80 matching lines @@
         ADD     pSrc,pSrc,pointStep
 
 
         // Loop on the sets
 
 radix4SetLoop\name :
 
 
 
         .ifeqs  "\inverse", "TRUE"
-            fmul   dZr1,dXr1,dW1[0]
-            fmul   dZi1,dXi1,dW1[0]
-            fmul   dZr2,dXr2,dW2[0]
-            fmul   dZi2,dXi2,dW2[0]
-            fmul   dZr3,dXr3,dW3[0]
-            fmul   dZi3,dXi3,dW3[0]
+            fmul   dZr1,dXr1,dW1s[0]
+            fmul   dZi1,dXi1,dW1s[0]
+            fmul   dZr2,dXr2,dW2s[0]
+            fmul   dZi2,dXi2,dW2s[0]
+            fmul   dZr3,dXr3,dW3s[0]
+            fmul   dZi3,dXi3,dW3s[0]
 
-            fmla   dZr1,dXi1,dW1[1]                // real part
-            fmls   dZi1,dXr1,dW1[1]                // imag part
+            fmla   dZr1,dXi1,dW1s[1]                // real part
+            fmls   dZi1,dXr1,dW1s[1]                // imag part
 
             //  data[1] for next iteration
             ld2     {dXr1,dXi1},[pSrc],pointStep
 
-            fmla   dZr2,dXi2,dW2[1]                // real part
-            fmls   dZi2,dXr2,dW2[1]                // imag part
+            fmla   dZr2,dXi2,dW2s[1]                // real part
+            fmls   dZi2,dXr2,dW2s[1]                // imag part
 
             //  data[2] for next iteration
             ld2     {dXr2,dXi2},[pSrc],pointStep
 
-            fmla   dZr3,dXi3,dW3[1]                // real part
-            fmls   dZi3,dXr3,dW3[1]                // imag part
+            fmla   dZr3,dXi3,dW3s[1]                // real part
+            fmls   dZi3,dXr3,dW3s[1]                // imag part
         .else
-            fmul   dZr1,dXr1,dW1[0]
-            fmul   dZi1,dXi1,dW1[0]
-            fmul   dZr2,dXr2,dW2[0]
-            fmul   dZi2,dXi2,dW2[0]
-            fmul   dZr3,dXr3,dW3[0]
-            fmul   dZi3,dXi3,dW3[0]
+            fmul   dZr1,dXr1,dW1s[0]
+            fmul   dZi1,dXi1,dW1s[0]
+            fmul   dZr2,dXr2,dW2s[0]
+            fmul   dZi2,dXi2,dW2s[0]
+            fmul   dZr3,dXr3,dW3s[0]
+            fmul   dZi3,dXi3,dW3s[0]
 
-            fmls   dZr1,dXi1,dW1[1]                // real part
-            fmla   dZi1,dXr1,dW1[1]                // imag part
+            fmls   dZr1,dXi1,dW1s[1]                // real part
+            fmla   dZi1,dXr1,dW1s[1]                // imag part
 
             //  data[1] for next iteration
             ld2     {dXr1,dXi1},[pSrc],pointStep
 
-            fmls   dZr2,dXi2,dW2[1]                // real part
-            fmla   dZi2,dXr2,dW2[1]                // imag part
+            fmls   dZr2,dXi2,dW2s[1]                // real part
+            fmla   dZi2,dXr2,dW2s[1]                // imag part
 
             //  data[2] for next iteration
             ld2     {dXr2,dXi2},[pSrc],pointStep
 
-            fmls   dZr3,dXi3,dW3[1]                // real part
-            fmla   dZi3,dXr3,dW3[1]                // imag part
+            fmls   dZr3,dXi3,dW3s[1]                // real part
+            fmla   dZi3,dXr3,dW3s[1]                // imag part
         .endif
 
         //  data[3] & update pSrc to data[0]
         // But don't read on the very last iteration because that reads past 
         // the end of pSrc. The last iteration is grpCount = 4, setCount = 2.
         cmp     grpCount, #4
         
         b.ne    skipUpdate\name
         cmp     setCount, #2
         b.ne    skipUpdate\name
@@ skipping 92 matching lines @@
             FFTSTAGE "FALSE","FALSE",FWD
         M_END
 
 
         M_START armSP_FFTInv_CToC_FC32_Radix4_OutOfPlace,,d15
             FFTSTAGE "FALSE","TRUE",INV
         M_END
 
 
         .end