arm64: clang assembler compatability

dl/sp/src/arm/arm64/armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S

 //
 //  Copyright (c) 2013 The WebRTC project authors. All Rights Reserved.
 //
 //  Use of this source code is governed by a BSD-style license
 //  that can be found in the LICENSE file in the root of the source
 //  tree. An additional intellectual property rights grant can be found
 //  in the file PATENTS.  All contributing project authors may
 //  be found in the AUTHORS file in the root of the source tree.
 //
 //  This is a modification of
@@ skipping 94 matching lines @@
 #define dY2     v4.2s
 #define dY3     v5.2s
 #define dW0     v6.2s
 #define dW1     v7.2s
 #define dW0Tmp  v10.2s
 #define dW1Neg  v11.2s
 
 #define dZip    v19.2s
 #define dZip8b  v19.8b
 #define half    v13.2s
+#define halfs   v13.s
 
         .macro FFTSTAGE scaled, inverse, name
 
         fmov    half, 0.5
 
         asr     size, subFFTNum, #1           // preserve the contents of N = subFFTNum
         lsl     step, subFFTNum, #2           // step = N/2 * 8 bytes
 
 
         // Z(k) = 1/2 {[F(k) +  F'(N/2-k)] +j*W^(-k) [F(k) -  F'(N/2-k)]}
         // Note: W^(k) is stored as negated value and also need to
         // conjugate the values from the table
 
         // Z(0) : no need of twiddle multiply
         // Z(0) = 1/2 { [F(0) +  F'(N/2)] +j [F(0) -  F'(N/2)] }
 
         ld1     {dX0},[pSrc],step
         ADD     pOut1,pOut,step               // pOut1 = pOut+ N/2*8 bytes
 
         ld1     {dX1},[pSrc], #8
         // twStep = 3N/8 * 8 bytes pointing to W^1
         SUB     twStep,step,size,LSL #1
 
         lsl     step1,size, #2                // step1 = N/4 * 8 = N/2*4 bytes
         SUB     step1,step1,#8                // (N/4-1)*8 bytes
 
         fadd    dY0,dX0,dX1                   // [b+d | a+c]
         fsub    dY1,dX0,dX1                   // [b-d | a-c]
-        fmul    dY0, dY0, half[0]
-        fmul    dY1, dY1, half[0]
+        fmul    dY0, dY0, halfs[0]
+        fmul    dY1, dY1, halfs[0]
 
         // dY0= [a-c | a+c] ;dY1= [b-d | b+d]
         // VZIP    dY0,dY1
         zip1    dZip,dY0,dY1
         zip2    dY1,dY0,dY1
         mov     dY08b, dZip8b
 
         fsub   dX0,dY0,dY1
         SUBS   size,size,#2
         fadd   dX1,dY0,dY1
@@ skipping 39 matching lines @@
         rev64   dX1i,dX1i
         SUBS    size,size,#4
 
 
         fsub    dT2,dX0r,dX1r                 // a-c
         fadd    dT3,dX0i,dX1i                 // b+d
         fadd    dT0,dX0r,dX1r                 // a+c
         fsub    dT1,dX0i,dX1i                 // b-d
         SUB     step1,step1,#8
 
-        fmul    dT2, dT2, half[0]
-        fmul    dT3, dT3, half[0]
+        fmul    dT2, dT2, halfs[0]
+        fmul    dT3, dT3, halfs[0]
 
-        fmul    dT0, dT0, half[0]
-        fmul    dT1, dT1, half[0]
+        fmul    dT0, dT0, halfs[0]
+        fmul    dT1, dT1, halfs[0]
 
         // VZIP    dW1r,dW1i
         // VZIP    dW0r,dW0i
         zip1    dZip, dW1r,dW1i
         zip2    dW1i,dW1r,dW1i
         mov     dW1r8b, dZip8b
         zip1    dZip,dW0r,dW0i
         zip2    dW0i,dW0r,dW0i
         mov     dW0r8b, dZip8b
 
@@ skipping 52 matching lines @@
 
 decrementScale\name :
 
         .endm
 
         M_START armSP_FFTInv_CCSToR_F32_preTwiddleRadix2,,d15
             FFTSTAGE "FALSE","TRUE",Inv
         M_END
 
         .end