Adds some floating point instructions to MIPS simulator, assembler, disassembler.

runtime/vm/constants_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_MIPS_H_
 #define VM_CONSTANTS_MIPS_H_
 
 namespace dart {
 
 enum Register {
@@ skipping 70 matching lines @@
   K0 = R26,
   K1 = R27,
 
   GP = R28,
   SP = R29,
   FP = R30,
   RA = R31,
 };
 
 
-// Values for double-precision floating point registers.
+// Values for floating point registers.
+// Double-precision values use register pairs.
 enum FRegister {
   F0  =  0,
   F1  =  1,
   F2  =  2,
   F3  =  3,
   F4  =  4,
   F5  =  5,
   F6  =  6,
   F7  =  7,
   F8  =  8,
@@ skipping 52 matching lines @@
 
 
 const RegList kAbiArgumentCpuRegs =
     (1 << A0) | (1 << A1) | (1 << A2) | (1 << A3);
 const RegList kAbiPreservedCpuRegs =
     (1 << S0) | (1 << S1) | (1 << S2) | (1 << S3) |
     (1 << S4) | (1 << S5) | (1 << S6) | (1 << S7);
 const int kAbiPreservedCpuRegCount = 8;
 
 
+// FPU registers 20 - 31 are preserved across calls.
+const FRegister kAbiFirstPreservedFpuReg = F20;
+const FRegister kAbiLastPreservedFpuReg =
+    static_cast<FRegister>(kNumberOfFRegisters - 1);
+
+// FPU registers 0 - 19 are not preserved across calls.
+const FRegister kDartFirstVolatileFpuReg = F0;
+const FRegister kDartLastVolatileFpuReg = F19;
+const int kDartVolatileFpuRegCount = 20;
+
 // Dart stack frame layout.
 static const int kLastParamSlotIndex = 3;
 static const int kFirstLocalSlotIndex = -2;
 
 
 // Values for the condition field.
 // There is no condition field on MIPS, but Conditions are used and passed
 // around by the intermediate language, so we need them here, too.
 enum Condition {
   EQ,  // equal
   NE,  // not equal
 };
 
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on the "Table 4.25 CPU Instruction Format Fields".
 enum InstructionFields {
   kOpcodeShift = 26,
   kOpcodeBits = 6,
   kRsShift = 21,
   kRsBits = 5,
+  kFmtShift = 21,
+  kFmtBits = 5,
   kRtShift = 16,
   kRtBits = 5,
+  kFtShift = 16,
+  kFtBits = 5,
   kRdShift = 11,
   kRdBits = 5,
+  kFsShift = 11,
+  kFsBits = 5,
   kSaShift = 6,
   kSaBits = 5,
+  kFdShift = 6,
+  kFdBits = 5,
   kFunctionShift = 0,
   kFunctionBits = 6,
+  kCop1FnShift = 0,
+  kCop1FnBits = 6,
+  kCop1SubShift = 21,
+  kCop1SubBits = 5,
   kImmShift = 0,
   kImmBits = 16,
   kInstrShift = 0,
   kInstrBits = 26,
   kBreakCodeShift = 6,
   kBreakCodeBits = 20,
 
   kBranchOffsetMask = 0x0000ffff,
 };
 
@@ skipping 112 matching lines @@
   TEQI = 12,
   TNEI = 14,
   BLTZAL = 16,
   BGEZAL = 17,
   BLTZALL = 18,
   BGEZALL = 19,
   SYNCI = 31,
 };
 
 
+enum Cop1Function {
+  COP1_ADD = 0,
+  COP1_MOV = 6,
+};
+
+enum Cop1Sub {
+  COP1_MF = 0,
+  COP1_MT = 4,
+};
+
+enum Format {
+  FMT_S = 16,
+  FMT_D = 17,
+  FMT_W = 20,
+  FMT_L = 21,
+  FMT_PS = 22,
+};
+
 class Instr {
  public:
   enum {
     kInstrSize = 4,
   };
 
   static const int32_t kBreakPointInstruction =
       (SPECIAL << kOpcodeShift) | (BREAK << kFunctionShift);
   static const int32_t kNopInstruction = 0;
   static const int32_t kStopMessageCode = 1;
@@ skipping 29 matching lines @@
   }
 
   inline Register RtField() const {
     return static_cast<Register>(Bits(kRtShift, kRtBits));
   }
 
   inline Register RdField() const {
     return static_cast<Register>(Bits(kRdShift, kRdBits));
   }
 
+  inline FRegister FsField() const {
+    return static_cast<FRegister>(Bits(kFsShift, kFsBits));
+  }
+
+  inline FRegister FtField() const {
+    return static_cast<FRegister>(Bits(kFtShift, kFtBits));
+  }
+
+  inline FRegister FdField() const {
+    return static_cast<FRegister>(Bits(kFdShift, kFdBits));
+  }
+
   inline int SaField() const {
     return Bits(kSaShift, kSaBits);
   }
 
   inline int32_t UImmField() const {
     return Bits(kImmShift, kImmBits);
   }
 
   inline int32_t SImmField() const {
     // Sign-extend the imm field.
     return (Bits(kImmShift, kImmBits) << (32 - kImmBits)) >> (32 - kImmBits);
   }
 
   inline int32_t BreakCodeField() const {
     return Bits(kBreakCodeShift, kBreakCodeBits);
   }
 
   inline SpecialFunction FunctionField() const {
     return static_cast<SpecialFunction>(Bits(kFunctionShift, kFunctionBits));
   }
 
   inline RtRegImm RegImmFnField() const {
     return static_cast<RtRegImm>(Bits(kRtShift, kRtBits));
   }
 
   inline bool IsBreakPoint() {
     return (OpcodeField() == SPECIAL) && (FunctionField() == BREAK);
   }
 
+  inline Cop1Function Cop1FunctionField() const {
+    return static_cast<Cop1Function>(Bits(kCop1FnShift, kCop1FnBits));
+  }
+
+  inline Cop1Sub Cop1SubField() const {
+    return static_cast<Cop1Sub>(Bits(kCop1SubShift, kCop1SubBits));
+  }
+
+  inline bool HasFormat() const {
+    return (OpcodeField() == COP1) && (Bit(25) == 1);
+  }
+
+  inline Format FormatField() const {
+    return static_cast<Format>(Bits(kFmtShift, kFmtBits));
+  }
+
   // Instructions are read out of a code stream. The only way to get a
   // reference to an instruction is to convert a pc. There is no way
   // to allocate or create instances of class Instr.
   // Use the At(pc) function to create references to Instr.
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_MIPS_H_