Adds some floating point instructions to MIPS simulator, assembler, disassembler.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 205 matching lines @@
     ASSERT(delay_slot_available_);
     ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
         Instr::kNopInstruction);
     buffer_.Remit<int32_t>();
     delay_slot_available_ = false;
     in_delay_slot_ = true;
     return this;
   }
 
   // CPU instructions in alphabetical order.
+  void addd(FRegister fd, FRegister fs, FRegister ft) {
+    ASSERT(EvenFPURegister(fd));
+    ASSERT(EvenFPURegister(fs));
+    ASSERT(EvenFPURegister(ft));
+    EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_ADD);
+  }
+
   void addiu(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsInt(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
 
+  void adds(FRegister fd, FRegister fs, FRegister ft) {
+    EmitFpuRType(COP1, FMT_S, ft, fs, fd, COP1_ADD);
+  }
+
   void addu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, ADDU);
   }
 
   void and_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, AND);
   }
 
   void andi(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
@@ skipping 139 matching lines @@
   }
 
   void lb(Register rt, const Address& addr) {
     EmitLoadStore(LB, rt, addr);
   }
 
   void lbu(Register rt, const Address& addr) {
     EmitLoadStore(LBU, rt, addr);
   }
 
+  void ldc1(FRegister ft, const Address& addr) {
+    ASSERT(EvenFPURegister(ft));
+    EmitFpuLoadStore(LDC1, ft, addr);
+  }
+
   void lh(Register rt, const Address& addr) {
     EmitLoadStore(LH, rt, addr);
   }
 
   void lhu(Register rt, const Address& addr) {
     EmitLoadStore(LHU, rt, addr);
   }
 
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
 
   void lw(Register rt, const Address& addr) {
     EmitLoadStore(LW, rt, addr);
   }
 
+  void lwc1(FRegister ft, const Address& addr) {
+    EmitFpuLoadStore(LWC1, ft, addr);
+  }
+
+  void mfc1(Register rt, FRegister fs) {
+    Emit(COP1 << kOpcodeShift |
+         COP1_MF << kCop1SubShift |
+         rt << kRtShift |
+         fs << kFsShift);
+  }
+
   void mfhi(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
   }
 
   void mflo(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
   }
 
   void mov(Register rd, Register rs) {
     or_(rd, rs, ZR);
   }
 
+  void movd(FRegister fd, FRegister fs) {
+    ASSERT(EvenFPURegister(fd));
+    ASSERT(EvenFPURegister(fs));
+    EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_MOV);
+  }
+
   void movn(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, MOVN);
   }
 
   void movz(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, MOVZ);
   }
 
+  void movs(FRegister fd, FRegister fs) {
+    EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_MOV);
+  }
+
+  void mtc1(Register rt, FRegister fs) {
+    Emit(COP1 << kOpcodeShift |
+         COP1_MT << kCop1SubShift |
+         rt << kRtShift |
+         fs << kFsShift);
+  }
+
   void mult(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULT);
   }
 
   void multu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULTU);
   }
 
   void nop() {
     Emit(Instr::kNopInstruction);
@@ skipping 10 matching lines @@
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
   void sb(Register rt, const Address& addr) {
     EmitLoadStore(SB, rt, addr);
   }
 
+  void sdc1(FRegister ft, const Address& addr) {
+    ASSERT(EvenFPURegister(ft));
+    EmitFpuLoadStore(SDC1, ft, addr);
+  }
+
   void sh(Register rt, const Address& addr) {
     EmitLoadStore(SH, rt, addr);
   }
 
   void sll(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
   }
 
   void sllv(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLLV);
@@ skipping 24 matching lines @@
   }
 
   void subu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SUBU);
   }
 
   void sw(Register rt, const Address& addr) {
     EmitLoadStore(SW, rt, addr);
   }
 
+  void swc1(FRegister ft, const Address& addr) {
+    EmitFpuLoadStore(SWC1, ft, addr);
+  }
+
   void xor_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, XOR);
   }
 
   // Macros in alphabetical order.
 
   // Addition of rs and rt with the result placed in rd.
   // After, ro < 0 if there was signed overflow, ro >= 0 otherwise.
   // rd and ro must not be TMP1 or TMP2.
   // ro must be different from all the other registers.
@@ skipping 45 matching lines @@
     if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, ZR, Immediate(value));
     } else {
       const uint16_t low = Utils::Low16Bits(value);
       const uint16_t high = Utils::High16Bits(value);
       lui(rd, Immediate(high));
       ori(rd, rd, Immediate(low));
     }
   }
 
+  void LoadImmediate(FRegister rd, double value) {
+    ASSERT(EvenFPURegister(rd));
+    const int64_t ival = bit_cast<uint64_t, double>(value);
+    const int32_t low = Utils::Low32Bits(ival);
+    const int32_t high = Utils::High32Bits(ival);
+    if (low != 0) {
+      LoadImmediate(TMP1, low);
+      mtc1(TMP1, rd);
+    } else {
+      mtc1(ZR, rd);
+    }
+
+    if (high != 0) {
+      LoadImmediate(TMP1, high);
+      mtc1(TMP1, static_cast<FRegister>(rd + 1));
+    } else {
+      mtc1(ZR, static_cast<FRegister>(rd + 1));
+    }
+  }
+
+  void LoadImmediate(FRegister rd, float value) {

[regis, 2013/04/12 17:08:56]

I am not sure we will need this one, since there is no single precision float
type in Dart.

[zra, 2013/04/12 17:19:26]

I'll keep it for now since I use it in some tests, but I won't add any more
single-precision instructions. I'll remove those instructions, tests and this
function later if it turns out they aren't needed.

+    const int32_t ival = bit_cast<int32_t, float>(value);
+    if (ival == 0) {
+      mtc1(ZR, rd);
+    } else {
+      LoadImmediate(TMP1, ival);
+      mtc1(TMP1, rd);
+    }
+  }
+
   void AddImmediate(Register rd, Register rs, int32_t value) {
     if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, rs, Immediate(value));
     } else {
       LoadImmediate(TMP1, value);
       addu(rd, rs, TMP1);
     }
   }
 
   void AddImmediate(Register rd, int32_t value) {
@@ skipping 149 matching lines @@
 
    private:
     intptr_t pc_offset_;
     const String& comment_;
 
     DISALLOW_COPY_AND_ASSIGN(CodeComment);
   };
 
   GrowableArray<CodeComment*> comments_;
 
+  bool EvenFPURegister(FRegister reg) {
+    return (static_cast<int>(reg) & 1) == 0;
+  }
+
   void Emit(int32_t value) {
     // Emitting an instruction clears the delay slot state.
     in_delay_slot_ = false;
     delay_slot_available_ = false;
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     buffer_.Emit<int32_t>(value);
   }
 
   // Encode CPU instructions according to the types specified in
   // Figures 4-1, 4-2 and 4-3 in VolI-A.
   void EmitIType(Opcode opcode,
                  Register rs,
                  Register rt,
                  uint16_t imm) {
     Emit(opcode << kOpcodeShift |
          rs << kRsShift |
          rt << kRtShift |
          imm);
   }
 
   void EmitLoadStore(Opcode opcode, Register rt,
                      const Address &addr) {
     Emit(opcode << kOpcodeShift |
          rt << kRtShift |
          addr.encoding());
   }
 
+  void EmitFpuLoadStore(Opcode opcode, FRegister ft,
+                        const Address &addr) {
+    Emit(opcode << kOpcodeShift |
+         ft << kFtShift |
+         addr.encoding());
+  }
+
   void EmitRegImmType(Opcode opcode,
                       Register rs,
                       RtRegImm code,
                       uint16_t imm) {
     Emit(opcode << kOpcodeShift |
          rs << kRsShift |
          code << kRtShift |
          imm);
   }
 
   void EmitJType(Opcode opcode, uint32_t destination) {
     UNIMPLEMENTED();
   }
 
   void EmitRType(Opcode opcode,
                  Register rs,
                  Register rt,
                  Register rd,
                  int sa,
                  SpecialFunction func) {
     ASSERT(Utils::IsUint(5, sa));
     Emit(opcode << kOpcodeShift |
          rs << kRsShift |
          rt << kRtShift |
          rd << kRdShift |
          sa << kSaShift |
          func << kFunctionShift);
   }
 
+  void EmitFpuRType(Opcode opcode,
+                    Format fmt,
+                    FRegister ft,
+                    FRegister fs,
+                    FRegister fd,
+                    Cop1Function func) {
+    Emit(opcode << kOpcodeShift |
+         fmt << kFmtShift |
+         ft << kFtShift |
+         fs << kFsShift |
+         fd << kFdShift |
+         func << kCop1FnShift);
+  }
+
   void EmitBranch(Opcode b, Register rs, Register rt, Label* label) {
     if (label->IsBound()) {
       // Relative destination from an instruction after the branch.
       const int32_t dest =
           label->Position() - (buffer_.Size() + Instr::kInstrSize);
       const uint16_t dest_off = EncodeBranchOffset(dest, 0);
       EmitIType(b, rs, rt, dest_off);
     } else {
       const int position = buffer_.Size();
       const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
@@ skipping 25 matching lines @@
     delay_slot_available_ = true;
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_