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Side by Side Diff: unittest/AssemblerX8664/GPRArith.cpp

Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix assembler unit tests. Fix register names. Code review changes. Rebase Created 5 years, 1 month ago
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1 //===- subzero/unittest/AssemblerX8664/GPRArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8664/GPRArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8664/TestUtil.h" 9 #include "AssemblerX8664/TestUtil.h"
10 10
(...skipping 23 matching lines...) Expand all
34 do { \ 34 do { \
35 static constexpr char TestString[] = \ 35 static constexpr char TestString[] = \
36 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ 36 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \
37 ", " #Value1 ")"; \ 37 ", " #Value1 ")"; \
38 const uint32_t T0 = allocateDword(); \ 38 const uint32_t T0 = allocateDword(); \
39 constexpr uint32_t V0 = 0xF00F00; \ 39 constexpr uint32_t V0 = 0xF00F00; \
40 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ 40 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \
41 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \ 41 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \
42 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ 42 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \
43 __ mov(IceType_i32, Encoded_GPR_##Dest(), Immediate(0)); \ 43 __ mov(IceType_i32, Encoded_GPR_##Dest(), Immediate(0)); \
44 __ setcc(Cond::Br_##C, RegX8664::getEncodedByteReg(Encoded_GPR_##Dest())); \ 44 __ setcc(Cond::Br_##C, Encoded_Bytereg_##Dest()); \
45 __ setcc(Cond::Br_##C, dwordAddress(T0)); \ 45 __ setcc(Cond::Br_##C, dwordAddress(T0)); \
46 \ 46 \
47 AssembledTest test = assemble(); \ 47 AssembledTest test = assemble(); \
48 test.setDwordTo(T0, V0); \ 48 test.setDwordTo(T0, V0); \
49 \ 49 \
50 test.run(); \ 50 test.run(); \
51 \ 51 \
52 ASSERT_EQ(IsTrue, test.Dest()) << TestString; \ 52 ASSERT_EQ(IsTrue, test.Dest()) << TestString; \
53 ASSERT_EQ((0xF00F00 | IsTrue), test.contentsOfDword(T0)) << TestString; \ 53 ASSERT_EQ((0xF00F00 | IsTrue), test.contentsOfDword(T0)) << TestString; \
54 reset(); \ 54 reset(); \
(...skipping 30 matching lines...) Expand all
85 TestSetCC(ge, Dest, 1u, Src0, 0x1u, Src1, 0x80000000u); \ 85 TestSetCC(ge, Dest, 1u, Src0, 0x1u, Src1, 0x80000000u); \
86 TestSetCC(ge, Dest, 0u, Src0, 0x80000000u, Src1, 0x1u); \ 86 TestSetCC(ge, Dest, 0u, Src0, 0x80000000u, Src1, 0x1u); \
87 TestSetCC(le, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \ 87 TestSetCC(le, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \
88 TestSetCC(le, Dest, 0u, Src0, 0x1u, Src1, 0x80000000u); \ 88 TestSetCC(le, Dest, 0u, Src0, 0x1u, Src1, 0x80000000u); \
89 } while (0) 89 } while (0)
90 90
91 TestImpl(r1, r2, r3); 91 TestImpl(r1, r2, r3);
92 TestImpl(r2, r3, r4); 92 TestImpl(r2, r3, r4);
93 TestImpl(r3, r4, r5); 93 TestImpl(r3, r4, r5);
94 TestImpl(r4, r5, r6); 94 TestImpl(r4, r5, r6);
95 TestImpl(r4, r6, r7);
95 TestImpl(r5, r6, r7); 96 TestImpl(r5, r6, r7);
96 TestImpl(r6, r7, r8); 97 TestImpl(r6, r7, r8);
97 TestImpl(r7, r8, r10); 98 TestImpl(r7, r8, r10);
98 TestImpl(r8, r10, r11); 99 TestImpl(r8, r10, r11);
99 TestImpl(r10, r11, r12); 100 TestImpl(r10, r11, r12);
100 TestImpl(r11, r12, r13); 101 TestImpl(r11, r12, r13);
101 TestImpl(r12, r13, r14); 102 TestImpl(r12, r13, r14);
102 TestImpl(r13, r14, r15); 103 TestImpl(r13, r14, r15);
103 TestImpl(r14, r15, r1); 104 TestImpl(r14, r15, r1);
104 TestImpl(r15, r1, r2); 105 TestImpl(r15, r1, r2);
(...skipping 1647 matching lines...) Expand 10 before | Expand all | Expand 10 after
1752 TEST_F(AssemblerX8664Test, Bt) { 1753 TEST_F(AssemblerX8664Test, Bt) {
1753 #define TestImpl(Dst, Value0, Src, Value1) \ 1754 #define TestImpl(Dst, Value0, Src, Value1) \
1754 do { \ 1755 do { \
1755 static constexpr char TestString[] = \ 1756 static constexpr char TestString[] = \
1756 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ")"; \ 1757 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ")"; \
1757 static constexpr uint32_t Expected = ((Value0) & (1u << (Value1))) != 0; \ 1758 static constexpr uint32_t Expected = ((Value0) & (1u << (Value1))) != 0; \
1758 \ 1759 \
1759 __ mov(IceType_i32, Encoded_GPR_##Dst(), Immediate(Value0)); \ 1760 __ mov(IceType_i32, Encoded_GPR_##Dst(), Immediate(Value0)); \
1760 __ mov(IceType_i32, Encoded_GPR_##Src(), Immediate(Value1)); \ 1761 __ mov(IceType_i32, Encoded_GPR_##Src(), Immediate(Value1)); \
1761 __ bt(Encoded_GPR_##Dst(), Encoded_GPR_##Src()); \ 1762 __ bt(Encoded_GPR_##Dst(), Encoded_GPR_##Src()); \
1762 __ setcc(Cond::Br_b, ByteRegister::Encoded_Reg_al); \ 1763 __ setcc(Cond::Br_b, ByteRegister::Encoded_8_Reg_al); \
1763 __ And(IceType_i32, Encoded_GPR_eax(), Immediate(0xFFu)); \ 1764 __ And(IceType_i32, Encoded_GPR_eax(), Immediate(0xFFu)); \
1764 \ 1765 \
1765 AssembledTest test = assemble(); \ 1766 AssembledTest test = assemble(); \
1766 test.run(); \ 1767 test.run(); \
1767 \ 1768 \
1768 ASSERT_EQ(Expected, test.eax()) << TestString; \ 1769 ASSERT_EQ(Expected, test.eax()) << TestString; \
1769 reset(); \ 1770 reset(); \
1770 } while (0) 1771 } while (0)
1771 1772
1772 TestImpl(r1, 0x08000000, r2, 27u); 1773 TestImpl(r1, 0x08000000, r2, 27u);
(...skipping 127 matching lines...) Expand 10 before | Expand all | Expand 10 after
1900 #undef TestImplValue 1901 #undef TestImplValue
1901 #undef TestImplSize 1902 #undef TestImplSize
1902 #undef TestImplRegAddr 1903 #undef TestImplRegAddr
1903 #undef TestImplRegReg 1904 #undef TestImplRegReg
1904 } 1905 }
1905 1906
1906 } // end of anonymous namespace 1907 } // end of anonymous namespace
1907 } // end of namespace Test 1908 } // end of namespace Test
1908 } // end of namespace X8664 1909 } // end of namespace X8664
1909 } // end of namespace Ice 1910 } // end of namespace Ice
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