Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 420 matching lines @@
                         &SpillAreaSizeBytes, &SpillAreaAlignmentBytes,
                         &LocalsSlotsAlignmentBytes, TargetVarHook);
   uint32_t LocalsSpillAreaSize = SpillAreaSizeBytes;
   SpillAreaSizeBytes += GlobalsSize;
 
   // Add push instructions for preserved registers.
   uint32_t NumCallee = 0;
   size_t PreservedRegsSizeBytes = 0;
   llvm::SmallBitVector Pushed(CalleeSaves.size());
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
-    // SizeT Canonical = RegX8632::getCanonicalReg(i); // TODO(stichnot)
-    SizeT Canonical = i;
+    SizeT Canonical = Traits::getBaseReg(i);
     if (CalleeSaves[i] && RegsUsed[i]) {
       Pushed[Canonical] = true;
     }
   }
   for (SizeT i = 0; i < Pushed.size(); ++i) {
     if (Pushed[i]) {
       ++NumCallee;
       PreservedRegsSizeBytes += typeWidthInBytes(IceType_i32);
       _push(getPhysicalRegister(i));
     }
@@ skipping 151 matching lines @@
     // add esp, SpillAreaSizeBytes
     if (SpillAreaSizeBytes)
       _add(esp, Ctx->getConstantInt32(SpillAreaSizeBytes));
   }
 
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
   llvm::SmallBitVector Popped(CalleeSaves.size());
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
-    // SizeT Canonical = RegX8632::getCanonicalReg(i); // TODO(stichnot)
-    SizeT Canonical = i;
+    SizeT Canonical = Traits::getBaseReg(i);
     if (CalleeSaves[i] && RegsUsed[i]) {
       Popped[Canonical] = true;
     }
   }
   for (SizeT i = 0; i < Popped.size(); ++i) {
     SizeT j = Popped.size() - i - 1;
+    SizeT Canonical = Traits::getBaseReg(j);
     if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame)
       continue;
     if (Popped[j]) {
-      _pop(getPhysicalRegister(j));
+      _pop(getPhysicalRegister(Canonical));
     }
   }
 
   if (!Ctx->getFlags().getUseSandboxing())
     return;
   // Change the original ret instruction into a sandboxed return sequence.
   // t:ecx = pop
   // bundle_lock
   // and t, ~31
   // jmp *t
@@ skipping 324 matching lines @@
 // case the high-level table has extra entries.
 #define X(tag, sizeLog2, align, elts, elty, str)                               \
   static_assert(_table1_##tag == _table2_##tag,                                \
                 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
 ICETYPE_TABLE
 #undef X
 } // end of namespace dummy3
 } // end of anonymous namespace
 
 } // end of namespace Ice