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Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix assembler unit tests. Fix register names. Code review changes. Rebase Created 5 years, 1 month ago
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1 //===- subzero/src/IceOperand.h - High-level operands -----------*- C++ -*-===// 1 //===- subzero/src/IceOperand.h - High-level operands -----------*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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342 342
343 /// RegWeight is a wrapper for a uint32_t weight value, with a special value 343 /// RegWeight is a wrapper for a uint32_t weight value, with a special value
344 /// that represents infinite weight, and an addWeight() method that ensures that 344 /// that represents infinite weight, and an addWeight() method that ensures that
345 /// W+infinity=infinity. 345 /// W+infinity=infinity.
346 class RegWeight { 346 class RegWeight {
347 public: 347 public:
348 RegWeight() = default; 348 RegWeight() = default;
349 explicit RegWeight(uint32_t Weight) : Weight(Weight) {} 349 explicit RegWeight(uint32_t Weight) : Weight(Weight) {}
350 RegWeight(const RegWeight &) = default; 350 RegWeight(const RegWeight &) = default;
351 RegWeight &operator=(const RegWeight &) = default; 351 RegWeight &operator=(const RegWeight &) = default;
352 const static uint32_t Inf = ~0; /// Force regalloc to give a register 352 constexpr static uint32_t Inf = ~0; /// Force regalloc to give a register
353 const static uint32_t Zero = 0; /// Force regalloc NOT to give a register 353 constexpr static uint32_t Zero = 0; /// Force regalloc NOT to give a register
354 const static uint32_t Max = Inf - 1; /// Max natural weight. 354 constexpr static uint32_t Max = Inf - 1; /// Max natural weight.
355 void addWeight(uint32_t Delta) { 355 void addWeight(uint32_t Delta) {
356 if (Delta == Inf) 356 if (Delta == Inf)
357 Weight = Inf; 357 Weight = Inf;
358 else if (Weight != Inf) 358 else if (Weight != Inf)
359 if (Utils::add_overflow(Weight, Delta, &Weight) || Weight == Inf) 359 if (Utils::add_overflow(Weight, Delta, &Weight) || Weight == Inf)
360 Weight = Max; 360 Weight = Max;
361 } 361 }
362 void addWeight(const RegWeight &Other) { addWeight(Other.Weight); } 362 void addWeight(const RegWeight &Other) { addWeight(Other.Weight); }
363 void setWeight(uint32_t Val) { Weight = Val; } 363 void setWeight(uint32_t Val) { Weight = Val; }
364 uint32_t getWeight() const { return Weight; } 364 uint32_t getWeight() const { return Weight; }
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465 bool getIgnoreLiveness() const { return IgnoreLiveness; } 465 bool getIgnoreLiveness() const { return IgnoreLiveness; }
466 466
467 int32_t getStackOffset() const { return StackOffset; } 467 int32_t getStackOffset() const { return StackOffset; }
468 void setStackOffset(int32_t Offset) { StackOffset = Offset; } 468 void setStackOffset(int32_t Offset) { StackOffset = Offset; }
469 /// Returns the variable's stack offset in symbolic form, to improve 469 /// Returns the variable's stack offset in symbolic form, to improve
470 /// readability in DecorateAsm mode. 470 /// readability in DecorateAsm mode.
471 IceString getSymbolicStackOffset(const Cfg *Func) const { 471 IceString getSymbolicStackOffset(const Cfg *Func) const {
472 return "lv$" + getName(Func); 472 return "lv$" + getName(Func);
473 } 473 }
474 474
475 static const int32_t NoRegister = -1; 475 static constexpr int32_t NoRegister = -1;
476 bool hasReg() const { return getRegNum() != NoRegister; } 476 bool hasReg() const { return getRegNum() != NoRegister; }
477 int32_t getRegNum() const { return RegNum; } 477 int32_t getRegNum() const { return RegNum; }
478 void setRegNum(int32_t NewRegNum) { 478 void setRegNum(int32_t NewRegNum) {
479 // Regnum shouldn't be set more than once. 479 // Regnum shouldn't be set more than once.
480 assert(!hasReg() || RegNum == NewRegNum); 480 assert(!hasReg() || RegNum == NewRegNum);
481 RegNum = NewRegNum; 481 RegNum = NewRegNum;
482 } 482 }
483 bool hasRegTmp() const { return getRegNumTmp() != NoRegister; } 483 bool hasRegTmp() const { return getRegNumTmp() != NoRegister; }
484 int32_t getRegNumTmp() const { return RegNumTmp; } 484 int32_t getRegNumTmp() const { return RegNumTmp; }
485 void setRegNumTmp(int32_t NewRegNum) { RegNumTmp = NewRegNum; } 485 void setRegNumTmp(int32_t NewRegNum) { RegNumTmp = NewRegNum; }
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500 void addLiveRange(InstNumberT Start, InstNumberT End) { 500 void addLiveRange(InstNumberT Start, InstNumberT End) {
501 assert(!getIgnoreLiveness()); 501 assert(!getIgnoreLiveness());
502 Live.addSegment(Start, End); 502 Live.addSegment(Start, End);
503 } 503 }
504 void trimLiveRange(InstNumberT Start) { Live.trim(Start); } 504 void trimLiveRange(InstNumberT Start) { Live.trim(Start); }
505 void untrimLiveRange() { Live.untrim(); } 505 void untrimLiveRange() { Live.untrim(); }
506 bool rangeEndsBefore(const Variable *Other) const { 506 bool rangeEndsBefore(const Variable *Other) const {
507 return Live.endsBefore(Other->Live); 507 return Live.endsBefore(Other->Live);
508 } 508 }
509 bool rangeOverlaps(const Variable *Other) const { 509 bool rangeOverlaps(const Variable *Other) const {
510 const bool UseTrimmed = true; 510 constexpr bool UseTrimmed = true;
511 return Live.overlaps(Other->Live, UseTrimmed); 511 return Live.overlaps(Other->Live, UseTrimmed);
512 } 512 }
513 bool rangeOverlapsStart(const Variable *Other) const { 513 bool rangeOverlapsStart(const Variable *Other) const {
514 const bool UseTrimmed = true; 514 constexpr bool UseTrimmed = true;
515 return Live.overlapsInst(Other->Live.getStart(), UseTrimmed); 515 return Live.overlapsInst(Other->Live.getStart(), UseTrimmed);
516 } 516 }
517 517
518 /// Creates a temporary copy of the variable with a different type. Used 518 /// Creates a temporary copy of the variable with a different type. Used
519 /// primarily for syntactic correctness of textual assembly emission. Note 519 /// primarily for syntactic correctness of textual assembly emission. Note
520 /// that only basic information is copied, in particular not IsArgument, 520 /// that only basic information is copied, in particular not IsArgument,
521 /// IsImplicitArgument, IgnoreLiveness, RegNumTmp, Live, LoVar, HiVar, 521 /// IsImplicitArgument, IgnoreLiveness, RegNumTmp, Live, LoVar, HiVar,
522 /// VarsReal. 522 /// VarsReal. If NewRegNum!=NoRegister, then that register assignment is made
523 Variable *asType(Type Ty); 523 /// instead of copying the existing assignment.
524 const Variable *asType(Type Ty, int32_t NewRegNum) const;
524 525
525 void emit(const Cfg *Func) const override; 526 void emit(const Cfg *Func) const override;
526 using Operand::dump; 527 using Operand::dump;
527 void dump(const Cfg *Func, Ostream &Str) const override; 528 void dump(const Cfg *Func, Ostream &Str) const override;
528 529
529 /// Return reg num of base register, if different from stack/frame register. 530 /// Return reg num of base register, if different from stack/frame register.
530 virtual int32_t getBaseRegNum() const { return NoRegister; } 531 virtual int32_t getBaseRegNum() const { return NoRegister; }
531 532
532 static bool classof(const Operand *Operand) { 533 static bool classof(const Operand *Operand) {
533 OperandKind Kind = Operand->getKind(); 534 OperandKind Kind = Operand->getKind();
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734 private: 735 private:
735 const Cfg *Func; 736 const Cfg *Func;
736 MetadataKind Kind; 737 MetadataKind Kind;
737 CfgVector<VariableTracking> Metadata; 738 CfgVector<VariableTracking> Metadata;
738 const static InstDefList NoDefinitions; 739 const static InstDefList NoDefinitions;
739 }; 740 };
740 741
741 } // end of namespace Ice 742 } // end of namespace Ice
742 743
743 #endif // SUBZERO_SRC_ICEOPERAND_H 744 #endif // SUBZERO_SRC_ICEOPERAND_H
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