Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceInstX86Base.h

 //===- subzero/src/IceInstX86Base.h - Generic x86 instructions -*- C++ -*--===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 129 matching lines @@
     IacaStart,
     IacaEnd
   };
 
   static const char *getWidthString(Type Ty);
   static const char *getFldString(Type Ty);
   static typename Traits::Cond::BrCond
   getOppositeCondition(typename Traits::Cond::BrCond Cond);
   void dump(const Cfg *Func) const override;
 
-  // Shared emit routines for common forms of instructions. See the definition
-  // of emitTwoAddress() for a description of ShiftHack.
+  // Shared emit routines for common forms of instructions.
   static void emitTwoAddress(const char *Opcode, const Inst *Inst,
-                             const Cfg *Func, bool ShiftHack = false);
+                             const Cfg *Func);
 
   static void
   emitIASGPRShift(const Cfg *Func, Type Ty, const Variable *Var,
                   const Operand *Src,
                   const typename Traits::Assembler::GPREmitterShiftOp &Emitter);
 
 protected:
   InstX86Base<Machine>(Cfg *Func, InstKindX86 Kind, SizeT Maxsrcs,
                        Variable *Dest)
       : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {}
@@ skipping 132 matching lines @@
 
 public:
   enum Mode { Near, Far };
 
   /// Create a conditional branch to a node.
   static InstX86Br *
   create(Cfg *Func, CfgNode *TargetTrue, CfgNode *TargetFalse,
          typename InstX86Base<Machine>::Traits::Cond::BrCond Condition,
          Mode Kind) {
     assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
-    const InstX86Label<Machine> *NoLabel = nullptr;
+    constexpr InstX86Label<Machine> *NoLabel = nullptr;
     return new (Func->allocate<InstX86Br>())
         InstX86Br(Func, TargetTrue, TargetFalse, NoLabel, Condition, Kind);
   }
   /// Create an unconditional branch to a node.
   static InstX86Br *create(Cfg *Func, CfgNode *Target, Mode Kind) {
-    const CfgNode *NoCondTarget = nullptr;
-    const InstX86Label<Machine> *NoLabel = nullptr;
+    constexpr CfgNode *NoCondTarget = nullptr;
+    constexpr InstX86Label<Machine> *NoLabel = nullptr;
     return new (Func->allocate<InstX86Br>())
         InstX86Br(Func, NoCondTarget, Target, NoLabel,
                   InstX86Base<Machine>::Traits::Cond::Br_None, Kind);
   }
   /// Create a non-terminator conditional branch to a node, with a fallthrough
   /// to the next instruction in the current node. This is used for switch
   /// lowering.
   static InstX86Br *
   create(Cfg *Func, CfgNode *Target,
          typename InstX86Base<Machine>::Traits::Cond::BrCond Condition,
          Mode Kind) {
     assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
-    const CfgNode *NoUncondTarget = nullptr;
-    const InstX86Label<Machine> *NoLabel = nullptr;
+    constexpr CfgNode *NoUncondTarget = nullptr;
+    constexpr InstX86Label<Machine> *NoLabel = nullptr;
     return new (Func->allocate<InstX86Br>())
         InstX86Br(Func, Target, NoUncondTarget, NoLabel, Condition, Kind);
   }
   /// Create a conditional intra-block branch (or unconditional, if
   /// Condition==Br_None) to a label in the current block.
   static InstX86Br *
   create(Cfg *Func, InstX86Label<Machine> *Label,
          typename InstX86Base<Machine>::Traits::Cond::BrCond Condition,
          Mode Kind) {
-    const CfgNode *NoCondTarget = nullptr;
-    const CfgNode *NoUncondTarget = nullptr;
+    constexpr CfgNode *NoCondTarget = nullptr;
+    constexpr CfgNode *NoUncondTarget = nullptr;
     return new (Func->allocate<InstX86Br>())
         InstX86Br(Func, NoCondTarget, NoUncondTarget, Label, Condition, Kind);
   }
   const CfgNode *getTargetTrue() const { return TargetTrue; }
   const CfgNode *getTargetFalse() const { return TargetFalse; }
   bool isNear() const { return Kind == Near; }
   bool optimizeBranch(const CfgNode *NextNode);
   uint32_t getEmitInstCount() const override {
     uint32_t Sum = 0;
     if (Label)
@@ skipping 287 matching lines @@
   InstX86BaseBinopGPRShift(const InstX86BaseBinopGPRShift &) = delete;
   InstX86BaseBinopGPRShift &
   operator=(const InstX86BaseBinopGPRShift &) = delete;
 
 public:
   using Base = InstX86BaseBinopGPRShift<Machine, K>;
 
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
-    const bool ShiftHack = true;
-    this->emitTwoAddress(Opcode, this, Func, ShiftHack);
+    this->emitTwoAddress(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     Type Ty = this->getDest()->getType();
     assert(this->getSrcSize() == 2);
     this->emitIASGPRShift(Func, Ty, this->getDest(), this->getSrc(1), Emitter);
   }
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 22 matching lines @@
   InstX86BaseBinopGPR() = delete;
   InstX86BaseBinopGPR(const InstX86BaseBinopGPR &) = delete;
   InstX86BaseBinopGPR &operator=(const InstX86BaseBinopGPR &) = delete;
 
 public:
   using Base = InstX86BaseBinopGPR<Machine, K>;
 
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
-    const bool ShiftHack = false;
-    this->emitTwoAddress(Opcode, this, Func, ShiftHack);
+    this->emitTwoAddress(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     Type Ty = this->getDest()->getType();
     assert(this->getSrcSize() == 2);
     emitIASRegOpTyGPR<Machine>(Func, Ty, this->getDest(), this->getSrc(1),
                                Emitter);
   }
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
@@ skipping 23 matching lines @@
   InstX86BaseBinopRMW() = delete;
   InstX86BaseBinopRMW(const InstX86BaseBinopRMW &) = delete;
   InstX86BaseBinopRMW &operator=(const InstX86BaseBinopRMW &) = delete;
 
 public:
   using Base = InstX86BaseBinopRMW<Machine, K>;
 
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
-    const bool ShiftHack = false;
-    this->emitTwoAddress(Opcode, this, Func, ShiftHack);
+    this->emitTwoAddress(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     Type Ty = this->getSrc(0)->getType();
     assert(this->getSrcSize() == 2);
     emitIASAsAddrOpTyGPR<Machine>(Func, Ty, this->getSrc(0), this->getSrc(1),
                                   Emitter);
   }
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
@@ skipping 26 matching lines @@
   InstX86BaseBinopXmm(const InstX86BaseBinopXmm &) = delete;
   InstX86BaseBinopXmm &operator=(const InstX86BaseBinopXmm &) = delete;
 
 public:
   using Base = InstX86BaseBinopXmm<Machine, K, NeedsElementType>;
 
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     this->validateVectorAddrMode();
-    const bool ShiftHack = false;
-    this->emitTwoAddress(Opcode, this, Func, ShiftHack);
+    this->emitTwoAddress(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     this->validateVectorAddrMode();
     Type Ty = this->getDest()->getType();
     if (NeedsElementType)
       Ty = typeElementType(Ty);
     assert(this->getSrcSize() == 2);
     emitIASRegOpTyXMM<Machine>(Func, Ty, this->getDest(), this->getSrc(1),
                                Emitter);
   }
@@ skipping 35 matching lines @@
   InstX86BaseBinopXmmShift &
   operator=(const InstX86BaseBinopXmmShift &) = delete;
 
 public:
   using Base = InstX86BaseBinopXmmShift<Machine, K, AllowAllTypes>;
 
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     this->validateVectorAddrMode();
-    const bool ShiftHack = false;
-    this->emitTwoAddress(Opcode, this, Func, ShiftHack);
+    this->emitTwoAddress(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     this->validateVectorAddrMode();
     Type Ty = this->getDest()->getType();
     assert(AllowAllTypes || isVectorType(Ty));
     Type ElementTy = typeElementType(Ty);
     assert(this->getSrcSize() == 2);
     emitIASXmmShift<Machine>(Func, ElementTy, this->getDest(), this->getSrc(1),
                              Emitter);
   }
@@ skipping 116 matching lines @@
 template <class Machine, typename InstX86Base<Machine>::InstKindX86 K>
 class InstX86BaseMovlike : public InstX86Base<Machine> {
   InstX86BaseMovlike() = delete;
   InstX86BaseMovlike(const InstX86BaseMovlike &) = delete;
   InstX86BaseMovlike &operator=(const InstX86BaseMovlike &) = delete;
 
 public:
   using Base = InstX86BaseMovlike<Machine, K>;
 
   bool isRedundantAssign() const override {
+    if (const auto *SrcVar = llvm::dyn_cast<const Variable>(this->getSrc(0))) {
+      if (SrcVar->hasReg() && this->Dest->hasReg()) {
+        // An assignment between physical registers is considered redundant if
+        // they have the same base register and the same encoding. E.g.:
+        //   mov cl, ecx ==> redundant
+        //   mov ch, ecx ==> not redundant due to different encodings
+        //   mov ch, ebp ==> not redundant due to different base registers
+        // TODO(stichnot): Don't consider "mov eax, eax" to be redundant when
+        // used in 64-bit mode to clear the upper half of rax.
+        int32_t SrcReg = SrcVar->getRegNum();
+        int32_t DestReg = this->Dest->getRegNum();
+        return (InstX86Base<Machine>::Traits::getEncoding(SrcReg) ==
+                InstX86Base<Machine>::Traits::getEncoding(DestReg)) &&
+               (InstX86Base<Machine>::Traits::getBaseReg(SrcReg) ==
+                InstX86Base<Machine>::Traits::getBaseReg(DestReg));
+      }
+    }
     return checkForRedundantAssign(this->getDest(), this->getSrc(0));
   }
   bool isVarAssign() const override {
     return llvm::isa<Variable>(this->getSrc(0));
   }
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     Str << Opcode << "." << this->getDest()->getType() << " ";
     this->dumpDest(Func);
     Str << ", ";
     this->dumpSources(Func);
   }
   static bool classof(const Inst *Inst) {
     return InstX86Base<Machine>::isClassof(Inst, InstX86Base<Machine>::K);
   }
 
 protected:
   InstX86BaseMovlike(Cfg *Func, Variable *Dest, Operand *Source)
       : InstX86Base<Machine>(Func, K, 1, Dest) {
     this->addSource(Source);
+    // For an integer assignment, make sure it's either a same-type assignment
+    // or a truncation.
+    assert(!isScalarIntegerType(Dest->getType()) ||
+           (typeWidthInBytes(Dest->getType()) <=
+            typeWidthInBytes(Source->getType())));
   }
 
   static const char *Opcode;
 };
 
 template <class Machine>
 class InstX86Bswap
     : public InstX86BaseInplaceopGPR<Machine, InstX86Base<Machine>::Bswap> {
 public:
   static InstX86Bswap *create(Cfg *Func, Operand *SrcDest) {
@@ skipping 2211 matching lines @@
           &InstX86Base<Machine>::Traits::Assembler::psrl};                     \
   }                                                                            \
   }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceInstX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEINSTX86BASE_H