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Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix assembler unit tests. Fix register names. Code review changes. Rebase Created 5 years, 1 month ago
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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
11 // form of x-macros. 11 // form of x-macros.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF 15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF
16 #define SUBZERO_SRC_ICEINSTX8664_DEF 16 #define SUBZERO_SRC_ICEINSTX8664_DEF
17 17
18 // NOTE: we use the 32bit register names for two reasons: 18 #include "IceRegList.h"
19 // (1) it makes it easier to implement the x86 assembler template. 19
20 // (2) when generating code, subzero defaults to using 32 bit registers, 20 // x86-64 ABI:
21 // so using the 32 bit register name would hopefully make this design 21 // Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11
22 // more explicit. 22 // Callee-save GPRs: rbx, rbp, r12, r13, r14, r15
23 // NOTE: esp is not considered isInt, to avoid register allocating it. 23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
24 // xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15
25 // Key to table columns:
26 // val: Enum value, when a specific register is needed during lowering.
27 // encode: Encoding in the integrated assembler.
28 // name: Name used for the external assembler.
29 // scratch: Scratch (caller-save) register.
30 // preserved: Preserved (callee-save) register.
31 // stackptr: This register is used as the stack pointer.
32 // frameptr: This register is used as the frame pointer if needed.
33 // isGPR: This is a GPR (integer-type).
34 // is64: This is a 64-bit GPR.
35 // is32: This is a 32-bit GPR.
36 // is16: This is a 16-bit GPR.
37 // is8: This is an 8-bit GPR.
38 // isXmm: This is an XMM register for FP and vector ops.
39 // is64To8: A 64-bit GPR truncable to 8-bit.
40 // is32To8: A 32-bit GPR truncable to 8-bit.
41 // is16To8: A 16-bit GPR truncable to 8-bit.
42 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
43 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
44 // aliases: List of register aliases, which need not include this register.
45 #define REGX8664_BYTEREG_TABLE \
46 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
47 isGPR,is64,is32,is16,is8, isXmm, \
48 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
49 /* 8-bit registers */ \
50 X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
51 REGLIST3(RegX8664, rax, eax, ax)) \
52 X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
53 REGLIST3(RegX8664, rcx, ecx, cx)) \
54 X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
55 REGLIST3(RegX8664, rdx, edx, dx)) \
56 X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
57 REGLIST3(RegX8664, rbx, ebx, bx)) \
58 X(Reg_spl, 4, "spl", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
59 REGLIST3(RegX8664, rsp, esp, sp)) \
60 X(Reg_bpl, 5, "bpl", Reg_ebp, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
61 REGLIST3(RegX8664, rbp, ebp, bp)) \
62 X(Reg_sil, 6, "sil", Reg_esi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
63 REGLIST3(RegX8664, rsi, esi, si)) \
64 X(Reg_dil, 7, "dil", Reg_edi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
65 REGLIST3(RegX8664, rdi, edi, di)) \
66 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
67 REGLIST3(RegX8664, r8, r8d, r8w)) \
68 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
69 REGLIST3(RegX8664, r9, r9d, r9w)) \
70 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
71 REGLIST3(RegX8664, r10, r10d, r10w)) \
72 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
73 REGLIST3(RegX8664, r11, r11d, r11w)) \
74 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
75 REGLIST3(RegX8664, r12, r12d, r12w)) \
76 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
77 REGLIST3(RegX8664, r13, r13d, r13w)) \
78 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
79 REGLIST3(RegX8664, r14, r14d, r14w)) \
80 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
81 REGLIST3(RegX8664, r15, r15d, r15w)) \
82 /* High 8-bit registers. None are allowed for register allocation. */ \
83 X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
84 REGLIST3(RegX8664, rax, eax, ax)) \
85 X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
86 REGLIST3(RegX8664, rcx, ecx, cx)) \
87 X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
88 REGLIST3(RegX8664, rdx, edx, dx)) \
89 X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
90 REGLIST3(RegX8664, rbx, ebx, bx)) \
91 /* End of 8-bit register set */
92 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
93 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
94 // isTrunc8Rcvr, isAhRcvr, aliases)
95
24 #define REGX8664_GPR_TABLE \ 96 #define REGX8664_GPR_TABLE \
25 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ 97 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
26 frameptr, isInt, isFP */ \ 98 isGPR,is64,is32,is16,is8, isXmm, \
27 X(Reg_eax, = 0, "rax", "eax" , "ax" , "al" , 1, 0, 0, 0, 1, 0) \ 99 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
28 X(Reg_ecx, = 1, "rcx", "ecx" , "cx" , "cl" , 1, 0, 0, 0, 1, 0) \ 100 /* 64-bit registers */ \
29 X(Reg_edx, = 2, "rdx", "edx" , "dx" , "dl" , 1, 0, 0, 0, 1, 0) \ 101 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
30 X(Reg_ebx, = 3, "rbx", "ebx" , "bx" , "bl" , 0, 1, 0, 0, 1, 0) \ 102 REGLIST4(RegX8664, eax, ax, al, ah)) \
31 X(Reg_esp, = 4, "rsp", "esp" , "sp" , "spl" , 0, 0, 1, 0, 0, 0) \ 103 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
32 X(Reg_ebp, = 5, "rbp", "ebp" , "bp" , "bpl" , 0, 0, 0, 1, 1, 0) \ 104 REGLIST4(RegX8664, ecx, cx, cl, ch)) \
33 X(Reg_esi, = 6, "rsi", "esi" , "si" , "sil" , 1, 0, 0, 0, 1, 0) \ 105 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
34 X(Reg_edi, = 7, "rdi", "edi" , "di" , "dil" , 1, 0, 0, 0, 1, 0) \ 106 REGLIST4(RegX8664, edx, dx, dl, dh)) \
35 X(Reg_r8d, = 8, "r8" , "r8d" , "r8w", "r8l" , 1, 0, 0, 0, 1, 0) \ 107 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
36 X(Reg_r9d, = 9, "r9" , "r9d" , "r9w", "r9l" , 1, 0, 0, 0, 1, 0) \ 108 REGLIST4(RegX8664, ebx, bx, bl, bh)) \
37 X(Reg_r10d, = 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \ 109 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
38 X(Reg_r11d, = 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \ 110 REGLIST3(RegX8664, esp, sp, spl)) \
39 X(Reg_r12d, = 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \ 111 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1, 1,1,0,0,0, 0, 0,0,0,0,0, \
40 X(Reg_r13d, = 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \ 112 REGLIST3(RegX8664, ebp, bp, bpl)) \
41 X(Reg_r14d, = 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \ 113 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
42 X(Reg_r15d, = 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0) 114 REGLIST3(RegX8664, esi, si, sil)) \
43 115 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
116 REGLIST3(RegX8664, edi, di, dil)) \
117 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
118 REGLIST3(RegX8664, r8d, r8w, r8l)) \
119 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
120 REGLIST3(RegX8664, r9d, r9w, r9l)) \
121 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
122 REGLIST3(RegX8664, r10d, r10w, r10l)) \
123 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
124 REGLIST3(RegX8664, r11d, r11w, r11l)) \
125 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
126 REGLIST3(RegX8664, r12d, r12w, r12l)) \
127 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
128 REGLIST3(RegX8664, r13d, r13w, r13l)) \
129 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
130 REGLIST3(RegX8664, r14d, r14w, r14l)) \
131 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
132 REGLIST3(RegX8664, r15d, r15w, r15l)) \
133 /* 32-bit registers */ \
134 X(Reg_eax, 0, "eax", Reg_eax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
135 REGLIST4(RegX8664, rax, ax, al, ah)) \
136 X(Reg_ecx, 1, "ecx", Reg_ecx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
137 REGLIST4(RegX8664, rcx, cx, cl, ch)) \
138 X(Reg_edx, 2, "edx", Reg_edx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
139 REGLIST4(RegX8664, rdx, dx, dl, dh)) \
140 X(Reg_ebx, 3, "ebx", Reg_ebx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
141 REGLIST4(RegX8664, rbx, bx, bl, bh)) \
142 X(Reg_esp, 4, "esp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
143 REGLIST3(RegX8664, rsp, sp, spl)) \
144 X(Reg_ebp, 5, "ebp", Reg_ebp, 0,1,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
145 REGLIST3(RegX8664, rbp, bp, bpl)) \
146 X(Reg_esi, 6, "esi", Reg_esi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
147 REGLIST3(RegX8664, rsi, si, sil)) \
148 X(Reg_edi, 7, "edi", Reg_edi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
149 REGLIST3(RegX8664, rdi, di, dil)) \
150 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
151 REGLIST3(RegX8664, r8, r8w, r8l)) \
152 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
153 REGLIST3(RegX8664, r9, r9w, r9l)) \
154 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1, 0,0,1,0,0, 0, 0,1,0,0,0, \
155 REGLIST3(RegX8664, r10, r10w, r10l)) \
156 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
157 REGLIST3(RegX8664, r11, r11w, r11l)) \
158 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
159 REGLIST3(RegX8664, r12, r12w, r12l)) \
160 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
161 REGLIST3(RegX8664, r13, r13w, r13l)) \
162 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
163 REGLIST3(RegX8664, r14, r14w, r14l)) \
164 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
165 REGLIST3(RegX8664, r15, r15w, r15l)) \
166 /* 16-bit registers */ \
167 X(Reg_ax, 0, "ax", Reg_eax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
168 REGLIST4(RegX8664, rax, eax, al, ah)) \
169 X(Reg_cx, 1, "cx", Reg_ecx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
170 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \
171 X(Reg_dx, 2, "dx", Reg_edx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
172 REGLIST4(RegX8664, rdx, edx, dl, dh)) \
173 X(Reg_bx, 3, "bx", Reg_ebx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
174 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \
175 X(Reg_sp, 4, "sp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
176 REGLIST3(RegX8664, rsp, esp, spl)) \
177 X(Reg_bp, 5, "bp", Reg_ebp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
178 REGLIST3(RegX8664, rbp, ebp, bpl)) \
179 X(Reg_si, 6, "si", Reg_esi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
180 REGLIST3(RegX8664, rsi, esi, sil)) \
181 X(Reg_di, 7, "di", Reg_edi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
182 REGLIST3(RegX8664, rdi, edi, dil)) \
183 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
184 REGLIST3(RegX8664, r8, r8d, r8l)) \
185 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
186 REGLIST3(RegX8664, r9, r9d, r9l)) \
187 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
188 REGLIST3(RegX8664, r10, r10d, r10l)) \
189 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
190 REGLIST3(RegX8664, r11, r11d, r11l)) \
191 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
192 REGLIST3(RegX8664, r12, r12d, r12l)) \
193 X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
194 REGLIST3(RegX8664, r13, r13d, r13l)) \
195 X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
196 REGLIST3(RegX8664, r14, r14d, r14l)) \
197 X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
198 REGLIST3(RegX8664, r15, r15d, r15l)) \
199 /* 8-bit registers */ \
200 REGX8664_BYTEREG_TABLE \
201 /* End of GPR register set */
202 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
203 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
204 // isTrunc8Rcvr, isAhRcvr, aliases)
205
206 // Note: It would be more appropriate to list the xmm register aliases as
207 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so
208 // we use REGLIST1() to redundantly assign the register itself as an alias.
44 #define REGX8664_XMM_TABLE \ 209 #define REGX8664_XMM_TABLE \
45 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ 210 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
46 frameptr, isInt, isFP */ \ 211 isGPR,is64,is32,is16,is8, isXmm, \
47 X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \ 212 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
48 X(Reg_xmm1, = 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \ 213 /* xmm registers */ \
49 X(Reg_xmm2, = 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \ 214 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
50 X(Reg_xmm3, = 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \ 215 REGLIST1(RegX8664, xmm0)) \
51 X(Reg_xmm4, = 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \ 216 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
52 X(Reg_xmm5, = 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \ 217 REGLIST1(RegX8664, xmm1)) \
53 X(Reg_xmm6, = 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \ 218 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
54 X(Reg_xmm7, = 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \ 219 REGLIST1(RegX8664, xmm2)) \
55 X(Reg_xmm8, = 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \ 220 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
56 X(Reg_xmm9, = 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \ 221 REGLIST1(RegX8664, xmm3)) \
57 X(Reg_xmm10, = 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \ 222 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
58 X(Reg_xmm11, = 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \ 223 REGLIST1(RegX8664, xmm4)) \
59 X(Reg_xmm12, = 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \ 224 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
60 X(Reg_xmm13, = 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \ 225 REGLIST1(RegX8664, xmm5)) \
61 X(Reg_xmm14, = 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \ 226 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
62 X(Reg_xmm15, = 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1) 227 REGLIST1(RegX8664, xmm6)) \
63 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, 228 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
64 // stackptr, frameptr, isI8, isInt, isFP) 229 REGLIST1(RegX8664, xmm7)) \
230 X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
231 REGLIST1(RegX8664, xmm8)) \
232 X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
233 REGLIST1(RegX8664, xmm9)) \
234 X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
235 REGLIST1(RegX8664, xmm10)) \
236 X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
237 REGLIST1(RegX8664, xmm11)) \
238 X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
239 REGLIST1(RegX8664, xmm12)) \
240 X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
241 REGLIST1(RegX8664, xmm13)) \
242 X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
243 REGLIST1(RegX8664, xmm14)) \
244 X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
245 REGLIST1(RegX8664, xmm15)) \
246 /* End of xmm register set */
247 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
248 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
249 // isTrunc8Rcvr, isAhRcvr, aliases)
65 250
66 // We also provide a combined table, so that there is a namespace where 251 // We also provide a combined table, so that there is a namespace where
67 // all of the registers are considered and have distinct numberings. 252 // all of the registers are considered and have distinct numberings.
68 // This is in contrast to the above, where the "encode" is based on how 253 // This is in contrast to the above, where the "encode" is based on how
69 // the register numbers will be encoded in binaries and values can overlap. 254 // the register numbers will be encoded in binaries and values can overlap.
70 #define REGX8664_TABLE \ 255 #define REGX8664_TABLE \
71 /* val, encode, name64, name, name16, name8, scratch, preserved, \
72 stackptr, frameptr, isInt, isFP */ \
73 REGX8664_GPR_TABLE \ 256 REGX8664_GPR_TABLE \
74 REGX8664_XMM_TABLE 257 REGX8664_XMM_TABLE
75 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, 258 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
76 // stackptr, frameptr, isI8, isInt, isFP) 259 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
77 260 // isTrunc8Rcvr, isAhRcvr, aliases)
78 #define REGX8664_TABLE_BOUNDS \
79 /* val , init */ \
80 X(Reg_GPR_First, = Reg_eax ) \
81 X(Reg_GPR_Last , = Reg_r15d ) \
82 X(Reg_XMM_First, = Reg_xmm0 ) \
83 X(Reg_XMM_Last , = Reg_xmm15)
84 // define X(val, init)
85
86 // We also need the encodings for the Byte registers (other info overlaps
87 // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh,
88 // bh registers to keep register selection simple.
89 #define REGX8664_BYTEREG_TABLE \
90 /* val , encode */ \
91 X(Reg_al , = 0) \
92 X(Reg_cl , = 1) \
93 X(Reg_dl , = 2) \
94 X(Reg_bl , = 3) \
95 X(Reg_spl , = 4) \
96 X(Reg_bpl , = 5) \
97 X(Reg_sil , = 6) \
98 X(Reg_dil , = 7) \
99 X(Reg_r8l , = 8) \
100 X(Reg_r9l , = 9) \
101 X(Reg_r10l, = 10) \
102 X(Reg_r11l, = 11) \
103 X(Reg_r12l, = 12) \
104 X(Reg_r13l, = 13) \
105 X(Reg_r14l, = 14) \
106 X(Reg_r15l, = 15)
107 //#define X(val, encode)
108 261
109 #define ICEINSTX8664BR_TABLE \ 262 #define ICEINSTX8664BR_TABLE \
110 /* enum value, encode, opposite, dump, emit */ \ 263 /* val, encode, opposite, dump, emit */ \
111 X(Br_o , = 0, Br_no , "o" , "jo" ) \ 264 X(Br_o, 0, Br_no, "o", "jo") \
112 X(Br_no , = 1, Br_o , "no", "jno") \ 265 X(Br_no, 1, Br_o, "no", "jno") \
113 X(Br_b , = 2, Br_ae , "b" , "jb" ) \ 266 X(Br_b, 2, Br_ae, "b", "jb") \
114 X(Br_ae , = 3, Br_b , "ae", "jae") \ 267 X(Br_ae, 3, Br_b, "ae", "jae") \
115 X(Br_e , = 4, Br_ne , "e" , "je" ) \ 268 X(Br_e, 4, Br_ne, "e", "je") \
116 X(Br_ne , = 5, Br_e , "ne", "jne") \ 269 X(Br_ne, 5, Br_e, "ne", "jne") \
117 X(Br_be , = 6, Br_a , "be", "jbe") \ 270 X(Br_be, 6, Br_a, "be", "jbe") \
118 X(Br_a , = 7, Br_be , "a" , "ja" ) \ 271 X(Br_a, 7, Br_be, "a", "ja") \
119 X(Br_s , = 8, Br_ns , "s" , "js" ) \ 272 X(Br_s, 8, Br_ns, "s", "js") \
120 X(Br_ns , = 9, Br_s , "ns", "jns") \ 273 X(Br_ns, 9, Br_s, "ns", "jns") \
121 X(Br_p , = 10, Br_np , "p" , "jp" ) \ 274 X(Br_p, 10, Br_np, "p", "jp") \
122 X(Br_np , = 11, Br_p , "np", "jnp") \ 275 X(Br_np, 11, Br_p, "np", "jnp") \
123 X(Br_l , = 12, Br_ge , "l" , "jl" ) \ 276 X(Br_l, 12, Br_ge, "l", "jl") \
124 X(Br_ge , = 13, Br_l , "ge", "jge") \ 277 X(Br_ge, 13, Br_l, "ge", "jge") \
125 X(Br_le , = 14, Br_g , "le", "jle") \ 278 X(Br_le, 14, Br_g, "le", "jle") \
126 X(Br_g , = 15, Br_le , "g" , "jg") 279 X(Br_g, 15, Br_le, "g", "jg")
127 //#define X(tag, encode, opp, dump, emit) 280 //#define X(val, encode, opp, dump, emit)
128 281
129 #define ICEINSTX8664CMPPS_TABLE \ 282 #define ICEINSTX8664CMPPS_TABLE \
130 /* enum value, emit */ \ 283 /* val, emit */ \
131 X(Cmpps_eq , "eq" ) \ 284 X(Cmpps_eq, "eq") \
132 X(Cmpps_lt , "lt" ) \ 285 X(Cmpps_lt, "lt") \
133 X(Cmpps_le , "le" ) \ 286 X(Cmpps_le, "le") \
134 X(Cmpps_unord, "unord") \ 287 X(Cmpps_unord, "unord") \
135 X(Cmpps_neq , "neq" ) \ 288 X(Cmpps_neq, "neq") \
136 X(Cmpps_nlt , "nlt" ) \ 289 X(Cmpps_nlt, "nlt") \
137 X(Cmpps_nle , "nle" ) \ 290 X(Cmpps_nle, "nle") \
138 X(Cmpps_ord , "ord" ) 291 X(Cmpps_ord, "ord")
139 //#define X(tag, emit) 292 //#define X(val, emit)
140 293
141 #define ICETYPEX8664_TABLE \ 294 #define ICETYPEX8664_TABLE \
142 /* tag , element type, cvt , sdss, pack, width, fld */ \ 295 /* tag , element type, cvt , sdss, pack, width, fld */ \
143 X(IceType_void , IceType_void, "?" , "" , "" , "" , "" ) \ 296 X(IceType_void, IceType_void, "?", "", "", "", "") \
144 X(IceType_i1 , IceType_void, "si", "" , "" , "b" , "" ) \ 297 X(IceType_i1, IceType_void, "si", "", "", "b", "") \
145 X(IceType_i8 , IceType_void, "si", "" , "" , "b" , "" ) \ 298 X(IceType_i8, IceType_void, "si", "", "", "b", "") \
146 X(IceType_i16 , IceType_void, "si", "" , "" , "w" , "" ) \ 299 X(IceType_i16, IceType_void, "si", "", "", "w", "") \
147 X(IceType_i32 , IceType_void, "si", "" , "" , "l" , "" ) \ 300 X(IceType_i32, IceType_void, "si", "", "", "l", "") \
148 X(IceType_i64 , IceType_void, "si", "" , "" , "q" , "" ) \ 301 X(IceType_i64, IceType_void, "si", "", "", "q", "") \
149 X(IceType_f32 , IceType_void, "ss", "ss", "d" , "" , "s") \ 302 X(IceType_f32, IceType_void, "ss", "ss", "d", "", "s") \
150 X(IceType_f64 , IceType_void, "sd", "sd", "q" , "" , "l") \ 303 X(IceType_f64, IceType_void, "sd", "sd", "q", "", "l") \
151 X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \ 304 X(IceType_v4i1, IceType_i32, "?", "", "d", "", "") \
152 X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \ 305 X(IceType_v8i1, IceType_i16, "?", "", "w", "", "") \
153 X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \ 306 X(IceType_v16i1, IceType_i8, "?", "", "b", "", "") \
154 X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \ 307 X(IceType_v16i8, IceType_i8, "?", "", "b", "", "") \
155 X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \ 308 X(IceType_v8i16, IceType_i16, "?", "", "w", "", "") \
156 X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \ 309 X(IceType_v4i32, IceType_i32, "dq", "", "d", "", "") \
157 X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" ) 310 X(IceType_v4f32, IceType_f32, "ps", "", "d", "", "")
158 //#define X(tag, elementty, cvt, sdss, pack, width, fld) 311 //#define X(tag, elementty, cvt, sdss, pack, width, fld)
159 312
160 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 313 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
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