Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 14 matching lines @@
 #include "IceRegistersX8632.h"
 #include "IceTargetLoweringX8632.h"
 #include "IceOperand.h"
 
 namespace Ice {
 
 namespace X86Internal {
 
 const MachineTraits<TargetX8632>::InstBrAttributesType
     MachineTraits<TargetX8632>::InstBrAttributes[] = {
-#define X(tag, encode, opp, dump, emit)                                        \
+#define X(val, encode, opp, dump, emit)                                        \
   { X8632::Traits::Cond::opp, dump, emit }                                     \
   ,
         ICEINSTX8632BR_TABLE
 #undef X
 };
 
 const MachineTraits<TargetX8632>::InstCmppsAttributesType
     MachineTraits<TargetX8632>::InstCmppsAttributes[] = {
-#define X(tag, emit)                                                           \
+#define X(val, emit)                                                           \
   { emit }                                                                     \
   ,
         ICEINSTX8632CMPPS_TABLE
 #undef X
 };
 
 const MachineTraits<TargetX8632>::TypeAttributesType
     MachineTraits<TargetX8632>::TypeAttributes[] = {
 #define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
   { cvt, sdss, pack, width, fld }                                              \
@@ skipping 48 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Str << "%" << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":";
   }
   // Emit as Offset(Base,Index,1<<Shift). Offset is emitted without the leading
   // '$'. Omit the (Base,Index,1<<Shift) part if Base==nullptr.
   if (!Offset) {
     // No offset, emit nothing.
-  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+  } else if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
     if (Base == nullptr || CI->getValue())
       // Emit a non-zero offset without a leading '$'.
       Str << CI->getValue();
-  } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
+  } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
     CR->emitWithoutPrefix(Func->getTarget());
   } else {
     llvm_unreachable("Invalid offset type for x86 mem operand");
   }
 
   if (Base || Index) {
     Str << "(";
     if (Base)
       Base->emit(Func);
     if (Index) {
@@ skipping 32 matching lines @@
       Index->dump(Func);
     else
       Index->dump(Str);
     Dumped = true;
   }
   // Pretty-print the Offset.
   bool OffsetIsZero = false;
   bool OffsetIsNegative = false;
   if (!Offset) {
     OffsetIsZero = true;
-  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+  } else if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
     OffsetIsZero = (CI->getValue() == 0);
     OffsetIsNegative = (static_cast<int32_t>(CI->getValue()) < 0);
   } else {
     assert(llvm::isa<ConstantRelocatable>(Offset));
   }
   if (Dumped) {
     if (!OffsetIsZero) {     // Suppress if Offset is known to be 0
       if (!OffsetIsNegative) // Suppress if Offset is known to be negative
         Str << "+";
       Offset->dump(Func, Str);
@@ skipping 13 matching lines @@
   }
 }
 
 MachineTraits<TargetX8632>::Address
 MachineTraits<TargetX8632>::X86OperandMem::toAsmAddress(
     MachineTraits<TargetX8632>::Assembler *Asm) const {
   int32_t Disp = 0;
   AssemblerFixup *Fixup = nullptr;
   // Determine the offset (is it relocatable?)
   if (getOffset()) {
-    if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
+    if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
       Disp = static_cast<int32_t>(CI->getValue());
     } else if (const auto CR =
                    llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
       Disp = CR->getOffset();
       Fixup = Asm->createFixup(RelFixup, CR);
     } else {
       llvm_unreachable("Unexpected offset type");
     }
   }
 
   // Now convert to the various possible forms.
   if (getBase() && getIndex()) {
-    return X8632::Traits::Address(
-        RegX8632::getEncodedGPR(getBase()->getRegNum()),
-        RegX8632::getEncodedGPR(getIndex()->getRegNum()),
-        X8632::Traits::ScaleFactor(getShift()), Disp, Fixup);
+    return X8632::Traits::Address(getEncodedGPR(getBase()->getRegNum()),
+                                  getEncodedGPR(getIndex()->getRegNum()),
+                                  X8632::Traits::ScaleFactor(getShift()), Disp,
+                                  Fixup);
   } else if (getBase()) {
-    return X8632::Traits::Address(
-        RegX8632::getEncodedGPR(getBase()->getRegNum()), Disp, Fixup);
+    return X8632::Traits::Address(getEncodedGPR(getBase()->getRegNum()), Disp,
+                                  Fixup);
   } else if (getIndex()) {
-    return X8632::Traits::Address(
-        RegX8632::getEncodedGPR(getIndex()->getRegNum()),
-        X8632::Traits::ScaleFactor(getShift()), Disp, Fixup);
+    return X8632::Traits::Address(getEncodedGPR(getIndex()->getRegNum()),
+                                  X8632::Traits::ScaleFactor(getShift()), Disp,
+                                  Fixup);
   } else {
     return X8632::Traits::Address(Disp, Fixup);
   }
 }
 
 MachineTraits<TargetX8632>::Address
 MachineTraits<TargetX8632>::VariableSplit::toAsmAddress(const Cfg *Func) const {
   assert(!Var->hasReg());
   const ::Ice::TargetLowering *Target = Func->getTarget();
   int32_t Offset =
       Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
-  return X8632::Traits::Address(
-      RegX8632::getEncodedGPR(Target->getFrameOrStackReg()), Offset,
-      AssemblerFixup::NoFixup);
+  return X8632::Traits::Address(getEncodedGPR(Target->getFrameOrStackReg()),
+                                Offset, AssemblerFixup::NoFixup);
 }
 
 void MachineTraits<TargetX8632>::VariableSplit::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(!Var->hasReg());
   // The following is copied/adapted from TargetX8632::emitVariable().
   const ::Ice::TargetLowering *Target = Func->getTarget();
-  const Type Ty = IceType_i32;
+  constexpr Type Ty = IceType_i32;
   int32_t Offset =
       Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
   if (Offset)
     Str << Offset;
   Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
 }
 
 void MachineTraits<TargetX8632>::VariableSplit::dump(const Cfg *Func,
                                                      Ostream &Str) const {
   if (!BuildDefs::dump())
@@ skipping 11 matching lines @@
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // namespace X86Internal
 } // end of namespace Ice
 
 X86INSTS_DEFINE_STATIC_DATA(TargetX8632)