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Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix assembler unit tests. Fix register names. Code review changes. Rebase Created 5 years, 1 month ago
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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of ARM32 instructions in the form of x-macros. 10 // This file defines properties of ARM32 instructions in the form of x-macros.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF 14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF
15 #define SUBZERO_SRC_ICEINSTARM32_DEF 15 #define SUBZERO_SRC_ICEINSTARM32_DEF
16 16
17 #include "IceRegList.h"
18
17 // NOTE: PC and SP are not considered isInt, to avoid register allocating. 19 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
18 // 20 //
19 // For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so 21 // For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so
20 // just reserve always. 22 // just reserve always.
21 // TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode). 23 // TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode).
22 // 24 //
23 // IP is not considered isInt to reserve it as a scratch register. A scratch 25 // IP is not considered isInt to reserve it as a scratch register. A scratch
24 // register is useful for expanding instructions post-register allocation. 26 // register is useful for expanding instructions post-register allocation.
25 // 27 //
26 // LR is not considered isInt to avoid being allocated as a register. It is 28 // LR is not considered isInt to avoid being allocated as a register. It is
27 // technically preserved, but save/restore is handled separately, based on 29 // technically preserved, but save/restore is handled separately, based on
28 // whether or not the function MaybeLeafFunc. 30 // whether or not the function MaybeLeafFunc.
29 31
30 // ALIASESn is a family of macros that we use to define register aliasing in
31 // ARM32. n indicates how many aliases are being provided to the macro. It
32 // assumes the parameters are register names declared in a namespace/class
33 // named RegARM32.
34 #define ALIASES1(r0) \
35 {RegARM32::r0}
36 #define ALIASES2(r0, r1) \
37 {RegARM32::r0, RegARM32::r1}
38 #define ALIASES3(r0, r1, r2) \
39 {RegARM32::r0, RegARM32::r1, RegARM32::r2}
40 #define ALIASES4(r0, r1, r2, r3) \
41 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3}
42 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \
43 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3, RegARM32::r4, \
44 RegARM32::r5,RegARM32::r6}
45
46
47 #define REGARM32_GPR_TABLE \ 32 #define REGARM32_GPR_TABLE \
48 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 33 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
49 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 34 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
50 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 35 X(Reg_r0, 0, "r0", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1)) \
51 ALIASES2(Reg_r0, Reg_r0r1)) \ 36 X(Reg_r1, 1, "r1", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1)) \
52 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 37 X(Reg_r2, 2, "r2", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3)) \
53 ALIASES2(Reg_r1, Reg_r0r1)) \ 38 X(Reg_r3, 3, "r3", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3)) \
54 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 39 X(Reg_r4, 4, "r4", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5)) \
55 ALIASES2(Reg_r2, Reg_r2r3)) \ 40 X(Reg_r5, 5, "r5", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5)) \
56 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 41 X(Reg_r6, 6, "r6", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7)) \
57 ALIASES2(Reg_r3, Reg_r2r3)) \ 42 X(Reg_r7, 7, "r7", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7)) \
58 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 43 X(Reg_r8, 8, "r8", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r8r9)) \
59 ALIASES2(Reg_r4, Reg_r4r5)) \ 44 X(Reg_r9, 9, "r9", 0,1,0,0, 0,0,0,0,0, REGLIST1(RegARM32, r8r9)) \
60 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 45 X(Reg_r10, 10, "r10", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r10fp)) \
61 ALIASES2(Reg_r5, Reg_r4r5)) \ 46 X(Reg_fp, 11, "fp", 0,1,0,1, 1,0,0,0,0, REGLIST1(RegARM32, r10fp)) \
62 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 47 X(Reg_ip, 12, "ip", 1,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, ip)) \
63 ALIASES2(Reg_r6, Reg_r6r7)) \ 48 X(Reg_sp, 13, "sp", 0,0,1,0, 0,0,0,0,0, REGLIST1(RegARM32, sp)) \
64 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 49 X(Reg_lr, 14, "lr", 0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, lr)) \
65 ALIASES2(Reg_r7, Reg_r6r7)) \ 50 X(Reg_pc, 15, "pc", 0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, pc))
66 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
67 ALIASES2(Reg_r8, Reg_r8r9)) \
68 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
69 ALIASES2(Reg_r9, Reg_r8r9)) \
70 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
71 ALIASES2(Reg_r10, Reg_r10fp)) \
72 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0, 0, \
73 ALIASES2(Reg_fp, Reg_r10fp)) \
74 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0, 0, \
75 ALIASES1(Reg_ip)) \
76 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \
77 ALIASES1(Reg_sp)) \
78 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
79 ALIASES1(Reg_lr)) \
80 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
81 ALIASES1(Reg_pc))
82 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 51 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
83 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 52 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
84 53
85 // The following defines a table with the available pairs of consecutive i32 54 // The following defines a table with the available pairs of consecutive i32
86 // GPRs starting at an even GPR that is not r14. Those are used to hold i64 55 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
87 // variables for atomic memory operations. If one of the registers in the pair 56 // variables for atomic memory operations. If one of the registers in the pair
88 // is preserved, then we mark the whole pair as preserved to help the register 57 // is preserved, then we mark the whole pair as preserved to help the register
89 // allocator. 58 // allocator.
90 #define REGARM32_I64PAIR_TABLE \ 59 #define REGARM32_I64PAIR_TABLE \
91 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 60 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
92 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 61 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
93 X(Reg_r0r1, 0, "r0, r1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 62 X(Reg_r0r1, 0, "r0, r1", 1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r0, r1)) \
94 ALIASES3(Reg_r0, Reg_r1, Reg_r0r1)) \ 63 X(Reg_r2r3, 2, "r2, r3", 1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r2, r3)) \
95 X(Reg_r2r3, 2, "r2, r3", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 64 X(Reg_r4r5, 4, "r4, r5", 0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r4, r5)) \
96 ALIASES3(Reg_r2, Reg_r3, Reg_r2r3)) \ 65 X(Reg_r6r7, 6, "r6, r7", 0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r6, r7)) \
97 X(Reg_r4r5, 4, "r4, r5", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 66 X(Reg_r8r9, 8, "r8, r9", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r8, r9)) \
98 ALIASES3(Reg_r4, Reg_r5, Reg_r4r5)) \ 67 X(Reg_r10fp, 10, "r10, fp", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r10, fp))
99 X(Reg_r6r7, 6, "r6, r7", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
100 ALIASES3(Reg_r6, Reg_r7, Reg_r6r7)) \
101 X(Reg_r8r9, 8, "r8, r9", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
102 ALIASES3(Reg_r8, Reg_r9, Reg_r8r9)) \
103 X(Reg_r10fp, 10, "r10, fp", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
104 ALIASES3(Reg_r10, Reg_fp, Reg_r10fp)) \
105 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 68 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
106 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 69 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
107 70
108 // S registers 0-15 are scratch, but 16-31 are preserved. 71 // S registers 0-15 are scratch, but 16-31 are preserved.
109 // Regenerate this with the following python script: 72 // Regenerate this with the following python script:
110 // 73 //
111 // def print_sregs(): 74 // def print_sregs():
112 // for i in xrange(0, 32): 75 // for i in xrange(0, 32):
113 // is_scratch = 1 if i < 16 else 0 76 // is_scratch = 1 if i < 16 else 0
114 // is_preserved = 1 if i >= 16 else 0 77 // is_preserved = 1 if i >= 16 else 0
115 // print (' X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' + 78 // print (' X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
116 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' + 79 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' +
117 // 'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' + 80 // 'REGLIST2(RegARM32, d{regnum:<2}, ' +
118 // 'Reg_q{regnum_q:<2})) \\').format( 81 // 'q{regnum_q:<2})) \\').format(
119 // regnum=i, regnum_d=i>>1, 82 // regnum=i, regnum_d=i>>1,
120 // regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved) 83 // regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
121 // 84 //
122 // print_sregs() 85 // print_sregs()
123 // 86 //
124 #define REGARM32_FP32_TABLE \ 87 #define REGARM32_FP32_TABLE \
125 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 88 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
126 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 89 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
127 X(Reg_s0 , 0 , "s0" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 90 X(Reg_s0, 0, "s0", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d0, q0)) \
128 ALIASES3(Reg_s0 , Reg_d0 , Reg_q0)) \ 91 X(Reg_s1, 1, "s1", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d0, q0)) \
129 X(Reg_s1 , 1 , "s1" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 92 X(Reg_s2, 2, "s2", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d1, q0)) \
130 ALIASES3(Reg_s1 , Reg_d0 , Reg_q0)) \ 93 X(Reg_s3, 3, "s3", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d1, q0)) \
131 X(Reg_s2 , 2 , "s2" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 94 X(Reg_s4, 4, "s4", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d2, q1)) \
132 ALIASES3(Reg_s2 , Reg_d1 , Reg_q0)) \ 95 X(Reg_s5, 5, "s5", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d2, q1)) \
133 X(Reg_s3 , 3 , "s3" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 96 X(Reg_s6, 6, "s6", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d3, q1)) \
134 ALIASES3(Reg_s3 , Reg_d1 , Reg_q0)) \ 97 X(Reg_s7, 7, "s7", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d3, q1)) \
135 X(Reg_s4 , 4 , "s4" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 98 X(Reg_s8, 8, "s8", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d4, q2)) \
136 ALIASES3(Reg_s4 , Reg_d2 , Reg_q1)) \ 99 X(Reg_s9, 9, "s9", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d4, q2)) \
137 X(Reg_s5 , 5 , "s5" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 100 X(Reg_s10, 10, "s10", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d5, q2)) \
138 ALIASES3(Reg_s5 , Reg_d2 , Reg_q1)) \ 101 X(Reg_s11, 11, "s11", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d5, q2)) \
139 X(Reg_s6 , 6 , "s6" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 102 X(Reg_s12, 12, "s12", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d6, q3)) \
140 ALIASES3(Reg_s6 , Reg_d3 , Reg_q1)) \ 103 X(Reg_s13, 13, "s13", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d6, q3)) \
141 X(Reg_s7 , 7 , "s7" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 104 X(Reg_s14, 14, "s14", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d7, q3)) \
142 ALIASES3(Reg_s7 , Reg_d3 , Reg_q1)) \ 105 X(Reg_s15, 15, "s15", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d7, q3)) \
143 X(Reg_s8 , 8 , "s8" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 106 X(Reg_s16, 16, "s16", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d8, q4)) \
144 ALIASES3(Reg_s8 , Reg_d4 , Reg_q2)) \ 107 X(Reg_s17, 17, "s17", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d8, q4)) \
145 X(Reg_s9 , 9 , "s9" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 108 X(Reg_s18, 18, "s18", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d9, q4)) \
146 ALIASES3(Reg_s9 , Reg_d4 , Reg_q2)) \ 109 X(Reg_s19, 19, "s19", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d9, q4)) \
147 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 110 X(Reg_s20, 20, "s20", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5)) \
148 ALIASES3(Reg_s10, Reg_d5 , Reg_q2)) \ 111 X(Reg_s21, 21, "s21", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5)) \
149 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 112 X(Reg_s22, 22, "s22", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5)) \
150 ALIASES3(Reg_s11, Reg_d5 , Reg_q2)) \ 113 X(Reg_s23, 23, "s23", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5)) \
151 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 114 X(Reg_s24, 24, "s24", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6)) \
152 ALIASES3(Reg_s12, Reg_d6 , Reg_q3)) \ 115 X(Reg_s25, 25, "s25", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6)) \
153 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 116 X(Reg_s26, 26, "s26", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6)) \
154 ALIASES3(Reg_s13, Reg_d6 , Reg_q3)) \ 117 X(Reg_s27, 27, "s27", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6)) \
155 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 118 X(Reg_s28, 28, "s28", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7)) \
156 ALIASES3(Reg_s14, Reg_d7 , Reg_q3)) \ 119 X(Reg_s29, 29, "s29", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7)) \
157 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 0, 1, 0, 0, \ 120 X(Reg_s30, 30, "s30", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7)) \
158 ALIASES3(Reg_s15, Reg_d7 , Reg_q3)) \ 121 X(Reg_s31, 31, "s31", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7))
159 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
160 ALIASES3(Reg_s16, Reg_d8 , Reg_q4)) \
161 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
162 ALIASES3(Reg_s17, Reg_d8 , Reg_q4)) \
163 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
164 ALIASES3(Reg_s18, Reg_d9 , Reg_q4)) \
165 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
166 ALIASES3(Reg_s19, Reg_d9 , Reg_q4)) \
167 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
168 ALIASES3(Reg_s20, Reg_d10, Reg_q5)) \
169 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
170 ALIASES3(Reg_s21, Reg_d10, Reg_q5)) \
171 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
172 ALIASES3(Reg_s22, Reg_d11, Reg_q5)) \
173 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
174 ALIASES3(Reg_s23, Reg_d11, Reg_q5)) \
175 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
176 ALIASES3(Reg_s24, Reg_d12, Reg_q6)) \
177 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
178 ALIASES3(Reg_s25, Reg_d12, Reg_q6)) \
179 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
180 ALIASES3(Reg_s26, Reg_d13, Reg_q6)) \
181 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
182 ALIASES3(Reg_s27, Reg_d13, Reg_q6)) \
183 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
184 ALIASES3(Reg_s28, Reg_d14, Reg_q7)) \
185 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
186 ALIASES3(Reg_s29, Reg_d14, Reg_q7)) \
187 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
188 ALIASES3(Reg_s30, Reg_d15, Reg_q7)) \
189 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
190 ALIASES3(Reg_s31, Reg_d15, Reg_q7))
191 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 122 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
192 // isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init) 123 // isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init)
193 124
194 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch 125 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
195 // (if supported by the D32 feature vs D16). D registers are defined in reverse 126 // (if supported by the D32 feature vs D16). D registers are defined in reverse
196 // order so that, during register allocation, Subzero will prefer higher D 127 // order so that, during register allocation, Subzero will prefer higher D
197 // registers. In processors supporting the D32 feature this will effectively 128 // registers. In processors supporting the D32 feature this will effectively
198 // cause double allocation to bias towards allocating "high" D registers, which 129 // cause double allocation to bias towards allocating "high" D registers, which
199 // do not alias any S registers. 130 // do not alias any S registers.
200 // 131 //
201 // Regenerate this with the following python script: 132 // Regenerate this with the following python script:
202 // def print_dregs(): 133 // def print_dregs():
203 // for i in xrange(31, 15, -1): 134 // for i in xrange(31, 15, -1):
204 // is_scratch = 1 if (i < 8 or i >= 16) else 0 135 // is_scratch = 1 if (i < 8 or i >= 16) else 0
205 // is_preserved = 1 if (8 <= i and i < 16) else 0 136 // is_preserved = 1 if (8 <= i and i < 16) else 0
206 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' + 137 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
207 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' + 138 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
208 // 'ALIASES(Reg_d{regnum:<2}, Reg_q{regnum_q:<2}) \\').format( 139 // 'REGLIST1(RegARM32, q{regnum_q:<2}) \\').format(
209 // regnum=i, regnum_q=i>>1, scratch=is_scratch, 140 // regnum=i, regnum_q=i>>1, scratch=is_scratch,
210 // preserved=is_preserved) 141 // preserved=is_preserved)
211 // for i in xrange(15, -1, -1): 142 // for i in xrange(15, -1, -1):
212 // is_scratch = 1 if (i < 8 or i >= 16) else 0 143 // is_scratch = 1 if (i < 8 or i >= 16) else 0
213 // is_preserved = 1 if (8 <= i and i < 16) else 0 144 // is_preserved = 1 if (8 <= i and i < 16) else 0
214 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' + 145 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
215 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' + 146 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
216 // 'ALIASES(Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' + 147 // 'REGLIST3(RegARM32, s{regnum_s0:<2}, s{regnum_s1:<2}, ' +
217 // 'Reg_d{regnum:<2}, Reg_q{regnum_q:<2})) \\').format( 148 // 'q{regnum_q:<2})) \\').format(
218 // regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i, 149 // regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i,
219 // regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved) 150 // regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved)
220 // 151 //
221 // print_dregs() 152 // print_dregs()
222 // 153 //
223 #define REGARM32_FP64_TABLE \ 154 #define REGARM32_FP64_TABLE \
224 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 155 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
225 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 156 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
226 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 157 X(Reg_d31, 31, "d31", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15)) \
227 ALIASES2(Reg_d31, Reg_q15)) \ 158 X(Reg_d30, 30, "d30", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15)) \
228 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 159 X(Reg_d29, 29, "d29", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14)) \
229 ALIASES2(Reg_d30, Reg_q15)) \ 160 X(Reg_d28, 28, "d28", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14)) \
230 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 161 X(Reg_d27, 27, "d27", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13)) \
231 ALIASES2(Reg_d29, Reg_q14)) \ 162 X(Reg_d26, 26, "d26", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13)) \
232 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 163 X(Reg_d25, 25, "d25", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12)) \
233 ALIASES2(Reg_d28, Reg_q14)) \ 164 X(Reg_d24, 24, "d24", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12)) \
234 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 165 X(Reg_d23, 23, "d23", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11)) \
235 ALIASES2(Reg_d27, Reg_q13)) \ 166 X(Reg_d22, 22, "d22", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11)) \
236 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 167 X(Reg_d21, 21, "d21", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10)) \
237 ALIASES2(Reg_d26, Reg_q13)) \ 168 X(Reg_d20, 20, "d20", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10)) \
238 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 169 X(Reg_d19, 19, "d19", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9)) \
239 ALIASES2(Reg_d25, Reg_q12)) \ 170 X(Reg_d18, 18, "d18", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9)) \
240 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 171 X(Reg_d17, 17, "d17", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8)) \
241 ALIASES2(Reg_d24, Reg_q12)) \ 172 X(Reg_d16, 16, "d16", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8)) \
242 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 173 X(Reg_d15, 15, "d15", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s30, s31, q7)) \
243 ALIASES2(Reg_d23, Reg_q11)) \ 174 X(Reg_d14, 14, "d14", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s28, s29, q7)) \
244 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 175 X(Reg_d13, 13, "d13", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s26, s27, q6)) \
245 ALIASES2(Reg_d22, Reg_q11)) \ 176 X(Reg_d12, 12, "d12", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s24, s25, q6)) \
246 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 177 X(Reg_d11, 11, "d11", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s22, s23, q5)) \
247 ALIASES2(Reg_d21, Reg_q10)) \ 178 X(Reg_d10, 10, "d10", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s20, s21, q5)) \
248 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 179 X(Reg_d9, 9, "d9", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s18, s19, q4)) \
249 ALIASES2(Reg_d20, Reg_q10)) \ 180 X(Reg_d8, 8, "d8", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s16, s17, q4)) \
250 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 181 X(Reg_d7, 7, "d7", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s14, s15, q3)) \
251 ALIASES2(Reg_d19, Reg_q9)) \ 182 X(Reg_d6, 6, "d6", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s12, s13, q3)) \
252 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 183 X(Reg_d5, 5, "d5", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s10, s11, q2)) \
253 ALIASES2(Reg_d18, Reg_q9)) \ 184 X(Reg_d4, 4, "d4", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s8, s9, q2)) \
254 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 185 X(Reg_d3, 3, "d3", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s6, s7, q1)) \
255 ALIASES2(Reg_d17, Reg_q8)) \ 186 X(Reg_d2, 2, "d2", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s4, s5, q1)) \
256 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 0, 1, 0, \ 187 X(Reg_d1, 1, "d1", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s2, s3, q0)) \
257 ALIASES2(Reg_d16, Reg_q8)) \ 188 X(Reg_d0, 0, "d0", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s0, s1, q0))
258 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
259 ALIASES4(Reg_s30, Reg_s31, Reg_d15, Reg_q7)) \
260 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
261 ALIASES4(Reg_s28, Reg_s29, Reg_d14, Reg_q7)) \
262 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
263 ALIASES4(Reg_s26, Reg_s27, Reg_d13, Reg_q6)) \
264 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
265 ALIASES4(Reg_s24, Reg_s25, Reg_d12, Reg_q6)) \
266 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
267 ALIASES4(Reg_s22, Reg_s23, Reg_d11, Reg_q5)) \
268 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
269 ALIASES4(Reg_s20, Reg_s21, Reg_d10, Reg_q5)) \
270 X(Reg_d9 , 9 , "d9", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
271 ALIASES4(Reg_s18, Reg_s19, Reg_d9 , Reg_q4)) \
272 X(Reg_d8 , 8 , "d8", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
273 ALIASES4(Reg_s16, Reg_s17, Reg_d8 , Reg_q4)) \
274 X(Reg_d7 , 7 , "d7", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
275 ALIASES4(Reg_s14, Reg_s15, Reg_d7 , Reg_q3)) \
276 X(Reg_d6 , 6 , "d6", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
277 ALIASES4(Reg_s12, Reg_s13, Reg_d6 , Reg_q3)) \
278 X(Reg_d5 , 5 , "d5", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
279 ALIASES4(Reg_s10, Reg_s11, Reg_d5 , Reg_q2)) \
280 X(Reg_d4 , 4 , "d4", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
281 ALIASES4(Reg_s8 , Reg_s9 , Reg_d4 , Reg_q2)) \
282 X(Reg_d3 , 3 , "d3", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
283 ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1)) \
284 X(Reg_d2 , 2 , "d2", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
285 ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1)) \
286 X(Reg_d1 , 1 , "d1", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
287 ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0)) \
288 X(Reg_d0 , 0 , "d0", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
289 ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0))
290 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 189 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
291 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 190 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
292 191
293 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch 192 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
294 // (if supported by the D32 feature). Q registers are defined in reverse order 193 // (if supported by the D32 feature). Q registers are defined in reverse order
295 // for the same reason as D registers. 194 // for the same reason as D registers.
296 // 195 //
297 // Regenerate this with the following python script: 196 // Regenerate this with the following python script:
298 // def print_qregs(): 197 // def print_qregs():
299 // for i in xrange(15, 7, -1): 198 // for i in xrange(15, 7, -1):
300 // is_scratch = 1 if (i < 4 or i >= 8) else 0 199 // is_scratch = 1 if (i < 4 or i >= 8) else 0
301 // is_preserved = 1 if (4 <= i and i < 8) else 0 200 // is_preserved = 1 if (4 <= i and i < 8) else 0
302 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' + 201 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
303 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, ALIASES(' + 202 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, REGLIST2(' +
304 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' + 203 // 'RegARM32, d{regnum_d0:<2}, d{regnum_d1:<2})) \\').format(
305 // 'Reg_q{regnum:<2})) \\').format(
306 // regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i, 204 // regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i,
307 // scratch=is_scratch, preserved=is_preserved) 205 // scratch=is_scratch, preserved=is_preserved)
308 // for i in xrange(7, -1, -1): 206 // for i in xrange(7, -1, -1):
309 // is_scratch = 1 if (i < 4 or i >= 8) else 0 207 // is_scratch = 1 if (i < 4 or i >= 8) else 0
310 // is_preserved = 1 if (4 <= i and i < 8) else 0 208 // is_preserved = 1 if (4 <= i and i < 8) else 0
311 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' + 209 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
312 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, ALIASES(' + 210 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, REGLIST6(' +
313 // 'Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' + 211 // 'RegARM32, s{regnum_s0:<2}, s{regnum_s1:<2}, ' +
314 // 'Reg_s{regnum_s2:<2}, Reg_s{regnum_s3:<2}, ' + 212 // 's{regnum_s2:<2}, s{regnum_s3:<2}, ' +
315 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' + 213 // 'd{regnum_d0:<2}, d{regnum_d1:<2})) \\').format(
316 // 'Reg_q{regnum:<2})) \\').format(
317 // regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2, 214 // regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2,
318 // regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1, 215 // regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1,
319 // regnum=i, scratch=is_scratch, preserved=is_preserved) 216 // regnum=i, scratch=is_scratch, preserved=is_preserved)
320 // 217 //
321 // print_qregs() 218 // print_qregs()
322 // 219 //
323 #define REGARM32_VEC128_TABLE \ 220 #define REGARM32_VEC128_TABLE \
324 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 221 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
325 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 222 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
326 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 223 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
327 ALIASES3(Reg_d30, Reg_d31, Reg_q15)) \ 224 REGLIST2(RegARM32, d30, d31)) \
328 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 225 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
329 ALIASES3(Reg_d28, Reg_d29, Reg_q14)) \ 226 REGLIST2(RegARM32, d28, d29)) \
330 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 227 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
331 ALIASES3(Reg_d26, Reg_d27, Reg_q13)) \ 228 REGLIST2(RegARM32, d26, d27)) \
332 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 229 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
333 ALIASES3(Reg_d24, Reg_d25, Reg_q12)) \ 230 REGLIST2(RegARM32, d24, d25)) \
334 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 231 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
335 ALIASES3(Reg_d22, Reg_d23, Reg_q11)) \ 232 REGLIST2(RegARM32, d22, d23)) \
336 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 233 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
337 ALIASES3(Reg_d20, Reg_d21, Reg_q10)) \ 234 REGLIST2(RegARM32, d20, d21)) \
338 X(Reg_q9 , 9 , "q9", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 235 X(Reg_q9, 9, "q9", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
339 ALIASES3(Reg_d18, Reg_d19, Reg_q9)) \ 236 REGLIST2(RegARM32, d18, d19)) \
340 X(Reg_q8 , 8 , "q8", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 237 X(Reg_q8, 8, "q8", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
341 ALIASES3(Reg_d16, Reg_d17, Reg_q8)) \ 238 REGLIST2(RegARM32, d16, d17)) \
342 X(Reg_q7 , 7 , "q7", 0, 1, 0, 0, 0, 0, 0, 0, 1, \ 239 X(Reg_q7, 7, "q7", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
343 ALIASES7(Reg_s28, Reg_s29, Reg_s30, Reg_s31, Reg_d14, Reg_d15, Reg_q7)) \ 240 REGLIST6(RegARM32, s28, s29, s30, s31, d14, d15)) \
344 X(Reg_q6 , 6 , "q6", 0, 1, 0, 0, 0, 0, 0, 0, 1, \ 241 X(Reg_q6, 6, "q6", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
345 ALIASES7(Reg_s24, Reg_s25, Reg_s26, Reg_s27, Reg_d12, Reg_d13, Reg_q6)) \ 242 REGLIST6(RegARM32, s24, s25, s26, s27, d12, d13)) \
346 X(Reg_q5 , 5 , "q5", 0, 1, 0, 0, 0, 0, 0, 0, 1, \ 243 X(Reg_q5, 5, "q5", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
347 ALIASES7(Reg_s20, Reg_s21, Reg_s22, Reg_s23, Reg_d10, Reg_d11, Reg_q5)) \ 244 REGLIST6(RegARM32, s20, s21, s22, s23, d10, d11)) \
348 X(Reg_q4 , 4 , "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1, \ 245 X(Reg_q4, 4, "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
349 ALIASES7(Reg_s16, Reg_s17, Reg_s18, Reg_s19, Reg_d8 , Reg_d9 , Reg_q4)) \ 246 REGLIST6(RegARM32, s16, s17, s18, s19, d8, d9)) \
350 X(Reg_q3 , 3 , "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 247 X(Reg_q3, 3, "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
351 ALIASES7(Reg_s12, Reg_s13, Reg_s14, Reg_s15, Reg_d6 , Reg_d7 , Reg_q3)) \ 248 REGLIST6(RegARM32, s12, s13, s14, s15, d6, d7)) \
352 X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 249 X(Reg_q2, 2, "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
353 ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2)) \ 250 REGLIST6(RegARM32, s8, s9, s10, s11, d4, d5)) \
354 X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 251 X(Reg_q1, 1, "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
355 ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1)) \ 252 REGLIST6(RegARM32, s4, s5, s6, s7, d2, d3)) \
356 X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1, \ 253 X(Reg_q0, 0, "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
357 ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0)) 254 REGLIST6(RegARM32, s0, s1, s2, s3, d0, d1))
358 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 255 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
359 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 256 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
360 257
361 // We also provide a combined table, so that there is a namespace where all of 258 // We also provide a combined table, so that there is a namespace where all of
362 // the registers are considered and have distinct numberings. This is in 259 // the registers are considered and have distinct numberings. This is in
363 // contrast to the above, where the "encode" is based on how the register 260 // contrast to the above, where the "encode" is based on how the register
364 // numbers will be encoded in binaries and values can overlap. 261 // numbers will be encoded in binaries and values can overlap.
365 #define REGARM32_TABLE \ 262 #define REGARM32_TABLE \
366 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 263 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
367 isFP32, isFP64, isVec128, alias_init */ \ 264 isFP32, isFP64, isVec128, alias_init */ \
(...skipping 50 matching lines...) Expand 10 before | Expand all | Expand 10 after
418 X(ASR, "asr") \ 315 X(ASR, "asr") \
419 X(ROR, "ror") \ 316 X(ROR, "ror") \
420 X(RRX, "rrx") 317 X(RRX, "rrx")
421 //#define X(tag, emit) 318 //#define X(tag, emit)
422 319
423 // Attributes for the condition code 4-bit encoding (that is independent of the 320 // Attributes for the condition code 4-bit encoding (that is independent of the
424 // APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE 321 // APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE
425 // is 1, but corresponds to Z = 0. 322 // is 1, but corresponds to Z = 0.
426 #define ICEINSTARM32COND_TABLE \ 323 #define ICEINSTARM32COND_TABLE \
427 /* enum value, encoding, opposite, emit */ \ 324 /* enum value, encoding, opposite, emit */ \
428 X(EQ, 0 , NE, "eq") /* equal */ \ 325 X(EQ, 0, NE, "eq") /* equal */ \
429 X(NE, 1 , EQ, "ne") /* not equal */ \ 326 X(NE, 1, EQ, "ne") /* not equal */ \
430 X(CS, 2 , CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \ 327 X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \
431 X(CC, 3 , CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \ 328 X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \
432 X(MI, 4 , PL, "mi") /* minus/negative */ \ 329 X(MI, 4, PL, "mi") /* minus/negative */ \
433 X(PL, 5 , MI, "pl") /* plus/positive or zero */ \ 330 X(PL, 5, MI, "pl") /* plus/positive or zero */ \
434 X(VS, 6 , VC, "vs") /* overflow (float unordered) */ \ 331 X(VS, 6, VC, "vs") /* overflow (float unordered) */ \
435 X(VC, 7 , VS, "vc") /* no overflow (float not unordered) */ \ 332 X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \
436 X(HI, 8 , LS, "hi") /* unsigned higher */ \ 333 X(HI, 8, LS, "hi") /* unsigned higher */ \
437 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \ 334 X(LS, 9, HI, "ls") /* unsigned lower or same */ \
438 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ 335 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
439 X(LT, 11, GE, "lt") /* signed less than */ \ 336 X(LT, 11, GE, "lt") /* signed less than */ \
440 X(GT, 12, LE, "gt") /* signed greater than */ \ 337 X(GT, 12, LE, "gt") /* signed greater than */ \
441 X(LE, 13, GT, "le") /* signed less than or equal */ \ 338 X(LE, 13, GT, "le") /* signed less than or equal */ \
442 X(AL, 14, kNone, "") /* always (unconditional) */ \ 339 X(AL, 14, kNone, "") /* always (unconditional) */ \
443 X(kNone, 15, kNone, "??") /* special condition / none */ 340 X(kNone, 15, kNone, "??") /* special condition / none */
444 //#define X(tag, encode, opp, emit) 341 //#define X(tag, encode, opp, emit)
445 342
446 #endif // SUBZERO_SRC_ICEINSTARM32_DEF 343 #endif // SUBZERO_SRC_ICEINSTARM32_DEF
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