Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 569 matching lines @@
       Node->getInsts().insert(I3, RMW);
     }
   }
   if (Func->isVerbose(IceV_RMW))
     Func->getContext()->unlockStr();
 }
 
 // Converts a ConstantInteger32 operand into its constant value, or
 // MemoryOrderInvalid if the operand is not a ConstantInteger32.
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
-  if (auto Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
+  if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 
 /// Determines whether the dest of a Load instruction can be folded into one of
 /// the src operands of a 2-operand instruction. This is true as long as the
 /// load dest matches exactly one of the binary instruction's src operands.
 /// Replaces Src0 or Src1 with LoadSrc if the answer is true.
 inline bool canFoldLoadIntoBinaryInst(Operand *LoadSrc, Variable *LoadDest,
                                       Operand *&Src0, Operand *&Src1) {
@@ skipping 14 matching lines @@
     while (!Context.atEnd()) {
       Variable *LoadDest = nullptr;
       Operand *LoadSrc = nullptr;
       Inst *CurInst = Context.getCur();
       Inst *Next = Context.getNextInst();
       // Determine whether the current instruction is a Load instruction or
       // equivalent.
       if (auto *Load = llvm::dyn_cast<InstLoad>(CurInst)) {
         // An InstLoad always qualifies.
         LoadDest = Load->getDest();
-        const bool DoLegalize = false;
+        constexpr bool DoLegalize = false;
         LoadSrc = formMemoryOperand(Load->getSourceAddress(),
                                     LoadDest->getType(), DoLegalize);
       } else if (auto *Intrin = llvm::dyn_cast<InstIntrinsicCall>(CurInst)) {
         // An AtomicLoad intrinsic qualifies as long as it has a valid memory
         // ordering, and can be implemented in a single instruction (i.e., not
         // i64 on x86-32).
         Intrinsics::IntrinsicID ID = Intrin->getIntrinsicInfo().ID;
         if (ID == Intrinsics::AtomicLoad &&
             (Traits::Is64Bit || Intrin->getDest()->getType() != IceType_i64) &&
             Intrinsics::isMemoryOrderValid(
                 ID, getConstantMemoryOrder(Intrin->getArg(1)))) {
           LoadDest = Intrin->getDest();
-          const bool DoLegalize = false;
+          constexpr bool DoLegalize = false;
           LoadSrc = formMemoryOperand(Intrin->getArg(0), LoadDest->getType(),
                                       DoLegalize);
         }
       }
       // A Load instruction can be folded into the following instruction only
       // if the following instruction ends the Load's Dest variable's live
       // range.
       if (LoadDest && Next && Next->isLastUse(LoadDest)) {
         assert(LoadSrc);
         Inst *NewInst = nullptr;
@@ skipping 77 matching lines @@
     // considered live upon function entry.  Otherwise it's possible to get
     // liveness validation errors for saving callee-save registers.
     Func->addImplicitArg(Reg);
     // Don't bother tracking the live range of a named physical register.
     Reg->setIgnoreLiveness();
   }
   return Reg;
 }
 
 template <class Machine>
-IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
-  return Traits::getRegName(RegNum, Ty);
+IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type) const {
+  return Traits::getRegName(RegNum);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << "%" << getRegName(Var->getRegNum(), Var->getType());
     return;
@@ skipping 42 matching lines @@
   if (Var->mustHaveReg()) {
     llvm_unreachable("Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (Var->getBaseRegNum() == Variable::NoRegister) {
     BaseRegNum = getFrameOrStackReg();
     if (!hasFramePointer())
       Offset += getStackAdjustment();
   }
-  return typename Traits::Address(
-      Traits::RegisterSet::getEncodedGPR(BaseRegNum), Offset);
+  return typename Traits::Address(Traits::getEncodedGPR(BaseRegNum), Offset);
 }
 
 /// Helper function for addProlog().
 ///
 /// This assumes Arg is an argument passed on the stack. This sets the frame
 /// offset for Arg and updates InArgsSizeBytes according to Arg's width. For an
 /// I64 arg that has been split into Lo and Hi components, it calls itself
 /// recursively on the components, taking care to handle Lo first because of the
 /// little-endian architecture. Lastly, this function generates an instruction
 /// to copy Arg into its assigned register if applicable.
@@ skipping 228 matching lines @@
       Src1 /= 2;
     } else {
       return false;
     }
   }
   // Lea optimization only works for i16 and i32 types, not i8.
   if (Ty != IceType_i16 && Ty != IceType_i32 && (Count3 || Count5 || Count9))
     return false;
   // Limit the number of lea/shl operations for a single multiply, to a
   // somewhat arbitrary choice of 3.
-  const uint32_t MaxOpsForOptimizedMul = 3;
+  constexpr uint32_t MaxOpsForOptimizedMul = 3;
   if (CountOps > MaxOpsForOptimizedMul)
     return false;
   _mov(T, Src0);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   for (uint32_t i = 0; i < Count9; ++i) {
-    const uint16_t Shift = 3; // log2(9-1)
+    constexpr uint16_t Shift = 3; // log2(9-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   for (uint32_t i = 0; i < Count5; ++i) {
-    const uint16_t Shift = 2; // log2(5-1)
+    constexpr uint16_t Shift = 2; // log2(5-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   for (uint32_t i = 0; i < Count3; ++i) {
-    const uint16_t Shift = 1; // log2(3-1)
+    constexpr uint16_t Shift = 1; // log2(3-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   if (Count2) {
     _shl(T, Ctx->getConstantInt(Ty, Count2));
   }
   if (Src1IsNegative)
     _neg(T);
   _mov(Dest, T);
   return true;
@@ skipping 131 matching lines @@
     }
   } else {
     // NON-CONSTANT CASES.
     Constant *BitTest = Ctx->getConstantInt32(0x20);
     typename Traits::Insts::Label *Label =
         Traits::Insts::Label::create(Func, this);
     // COMMON PREFIX OF: a=b SHIFT_OP c ==>
     //   t1:ecx = c.lo & 0xff
     //   t2 = b.lo
     //   t3 = b.hi
-    _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
+    T_1 = makeReg(IceType_i8, Traits::RegisterSet::Reg_cl);
+    _mov(T_1, Src1Lo);
     _mov(T_2, Src0Lo);
     _mov(T_3, Src0Hi);
     switch (Op) {
     default:
       assert(0 && "non-shift op");
       break;
     case InstArithmetic::Shl: {
       // a=b<<c ==>
       //   t3 = shld t3, t2, t1
       //   t2 = shl t2, t1
@@ skipping 87 matching lines @@
   }
   if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
     // These x86-32 helper-call-involved instructions are lowered in this
     // separate switch. This is because loOperand() and hiOperand() may insert
     // redundant instructions for constant blinding and pooling. Such redundant
     // instructions will fail liveness analysis under -Om1 setting. And,
     // actually these arguments do not need to be processed with loOperand()
     // and hiOperand() to be used.
     switch (Inst->getOp()) {
     case InstArithmetic::Udiv: {
-      const SizeT MaxSrcs = 2;
+      constexpr SizeT MaxSrcs = 2;
       InstCall *Call = makeHelperCall(H_udiv_i64, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       Call->addArg(Inst->getSrc(1));
       lowerCall(Call);
       return;
     }
     case InstArithmetic::Sdiv: {
-      const SizeT MaxSrcs = 2;
+      constexpr SizeT MaxSrcs = 2;
       InstCall *Call = makeHelperCall(H_sdiv_i64, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       Call->addArg(Inst->getSrc(1));
       lowerCall(Call);
       return;
     }
     case InstArithmetic::Urem: {
-      const SizeT MaxSrcs = 2;
+      constexpr SizeT MaxSrcs = 2;
       InstCall *Call = makeHelperCall(H_urem_i64, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       Call->addArg(Inst->getSrc(1));
       lowerCall(Call);
       return;
     }
     case InstArithmetic::Srem: {
-      const SizeT MaxSrcs = 2;
+      constexpr SizeT MaxSrcs = 2;
       InstCall *Call = makeHelperCall(H_srem_i64, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       Call->addArg(Inst->getSrc(1));
       lowerCall(Call);
       return;
     }
     default:
       break;
     }
 
@@ skipping 160 matching lines @@
         // pmuludq T1, Src1
         // # T2 = {Src0[1] * Src1[1], Src0[3] * Src1[3]}
         // pmuludq T2, T3
         // # T1 = {lo(T1[0]), lo(T1[2]), lo(T2[0]), lo(T2[2])}
         // shufps  T1, T2, {0,2,0,2}
         // pshufd  T4, T1, {0,2,1,3}
         // movups  Dest, T4
 
         // Mask that directs pshufd to create a vector with entries
         // Src[1, 0, 3, 0]
-        const unsigned Constant1030 = 0x31;
+        constexpr unsigned Constant1030 = 0x31;
         Constant *Mask1030 = Ctx->getConstantInt32(Constant1030);
         // Mask that directs shufps to create a vector with entries
         // Dest[0, 2], Src[0, 2]
-        const unsigned Mask0202 = 0x88;
+        constexpr unsigned Mask0202 = 0x88;
         // Mask that directs pshufd to create a vector with entries
         // Src[0, 2, 1, 3]
-        const unsigned Mask0213 = 0xd8;
+        constexpr unsigned Mask0213 = 0xd8;
         Variable *T1 = makeReg(IceType_v4i32);
         Variable *T2 = makeReg(IceType_v4i32);
         Variable *T3 = makeReg(IceType_v4i32);
         Variable *T4 = makeReg(IceType_v4i32);
         _movp(T1, Src0);
         _pshufd(T2, Src0, Mask1030);
         _pshufd(T3, Src1, Mask1030);
         _pmuludq(T1, Src1);
         _pmuludq(T2, T3);
         _shufps(T1, T2, Ctx->getConstantInt32(Mask0202));
@@ skipping 74 matching lines @@
     _mov(T, Src0);
     _sub(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Mul:
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
       if (optimizeScalarMul(Dest, Src0, C->getValue()))
         return;
     }
     // The 8-bit version of imul only allows the form "imul r/m8" where T must
-    // be in eax.
+    // be in al.
     if (isByteSizedArithType(Dest->getType())) {
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T, Src0, Traits::RegisterSet::Reg_al);
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       _imul(T, Src0 == Src1 ? T : Src1);
       _mov(Dest, T);
     } else if (auto *ImmConst = llvm::dyn_cast<ConstantInteger32>(Src1)) {
       T = makeReg(Dest->getType());
       _imul_imm(T, Src0, ImmConst);
       _mov(Dest, T);
     } else {
       _mov(T, Src0);
       _imul(T, Src0 == Src1 ? T : Src1);
       _mov(Dest, T);
     }
     break;
   case InstArithmetic::Shl:
     _mov(T, Src0);
-    if (!llvm::isa<ConstantInteger32>(Src1))
-      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
+    if (!llvm::isa<ConstantInteger32>(Src1)) {
+      Variable *Cl = makeReg(IceType_i8, Traits::RegisterSet::Reg_cl);
+      _mov(Cl, Src1);
+      Src1 = Cl;
+    }
     _shl(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Lshr:
     _mov(T, Src0);
-    if (!llvm::isa<ConstantInteger32>(Src1))
-      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
+    if (!llvm::isa<ConstantInteger32>(Src1)) {
+      Variable *Cl = makeReg(IceType_i8, Traits::RegisterSet::Reg_cl);
+      _mov(Cl, Src1);
+      Src1 = Cl;
+    }
     _shr(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Ashr:
     _mov(T, Src0);
-    if (!llvm::isa<ConstantInteger32>(Src1))
-      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
+    if (!llvm::isa<ConstantInteger32>(Src1)) {
+      Variable *Cl = makeReg(IceType_i8, Traits::RegisterSet::Reg_cl);
+      _mov(Cl, Src1);
+      Src1 = Cl;
+    }
     _sar(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Udiv:
     // div and idiv are the few arithmetic operators that do not allow
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
       // For 8-bit unsigned division we need to zero-extend al into ah. A mov
       // $0, %ah (or xor %ah, %ah) would work just fine, except that the x86-64
       // assembler refuses to encode %ah (encoding %spl with a REX prefix
       // instead.) Accessing %ah in 64-bit is "tricky" as you can't encode %ah
       // with any other 8-bit register except for %a[lh], %b[lh], %c[lh], and
       // d[%lh], which means the X86 target lowering (and the register
       // allocator) would have to be aware of this restriction. For now, we
       // simply zero %eax completely, and move the dividend into %al.
       Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
       Context.insert(InstFakeDef::create(Func, T_eax));
       _xor(T_eax, T_eax);
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T, Src0, Traits::RegisterSet::Reg_al);
       _div(T, Src1, T);
       _mov(Dest, T);
       Context.insert(InstFakeUse::create(Func, T_eax));
     } else {
-      Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
-      _mov(T_edx, Zero, Traits::RegisterSet::Reg_edx);
+      Type Ty = Dest->getType();
+      uint32_t Eax = Traits::RegisterSet::Reg_eax;
+      uint32_t Edx = Traits::RegisterSet::Reg_edx;
+      switch (Ty) {
+      default:
+        llvm_unreachable("Bad type for udiv");
+      // fallthrough
+      case IceType_i32:
+        break;
+      case IceType_i16:
+        Eax = Traits::RegisterSet::Reg_ax;
+        Edx = Traits::RegisterSet::Reg_dx;
+        break;
+      }
+      Constant *Zero = Ctx->getConstantZero(Ty);
+      _mov(T, Src0, Eax);
+      _mov(T_edx, Zero, Edx);
       _div(T, Src1, T_edx);
       _mov(Dest, T);
     }
     break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
@@ skipping 21 matching lines @@
             _shr(T, Ctx->getConstantInt(Ty, TypeWidth - LogDiv));
             _add(T, Src0);
             _sar(T, Ctx->getConstantInt(Ty, LogDiv));
           }
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    if (isByteSizedArithType(Dest->getType())) {
+    switch (Type Ty = Dest->getType()) {
+    default:
+      llvm_unreachable("Bad type for sdiv");
+    // fallthrough
+    case IceType_i32:
+      T_edx = makeReg(Ty, Traits::RegisterSet::Reg_edx);
       _mov(T, Src0, Traits::RegisterSet::Reg_eax);
-      _cbwdq(T, T);
-      _idiv(T, Src1, T);
-      _mov(Dest, T);
-    } else {
-      T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
-      _cbwdq(T_edx, T);
-      _idiv(T, Src1, T_edx);
-      _mov(Dest, T);
+      break;
+    case IceType_i16:
+      T_edx = makeReg(Ty, Traits::RegisterSet::Reg_dx);
+      _mov(T, Src0, Traits::RegisterSet::Reg_ax);
+      break;
+    case IceType_i8:
+      T_edx = makeReg(IceType_i16, Traits::RegisterSet::Reg_ax);
+      _mov(T, Src0, Traits::RegisterSet::Reg_al);
+      break;
     }
+    _cbwdq(T_edx, T);
+    _idiv(T, Src1, T_edx);
+    _mov(Dest, T);
     break;
   case InstArithmetic::Urem:
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
       Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
       Context.insert(InstFakeDef::create(Func, T_eax));
       _xor(T_eax, T_eax);
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T, Src0, Traits::RegisterSet::Reg_al);
       _div(T, Src1, T);
       // shr $8, %eax shifts ah (i.e., the 8 bit remainder) into al. We don't
       // mov %ah, %al because it would make x86-64 codegen more complicated. If
       // this ever becomes a problem we can introduce a pseudo rem instruction
       // that returns the remainder in %al directly (and uses a mov for copying
       // %ah to %al.)
       static constexpr uint8_t AlSizeInBits = 8;
       _shr(T_eax, Ctx->getConstantInt8(AlSizeInBits));
       _mov(Dest, T);
       Context.insert(InstFakeUse::create(Func, T_eax));
     } else {
-      Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      T_edx = makeReg(Dest->getType(), Traits::RegisterSet::Reg_edx);
+      Type Ty = Dest->getType();
+      uint32_t Eax = Traits::RegisterSet::Reg_eax;
+      uint32_t Edx = Traits::RegisterSet::Reg_edx;
+      switch (Ty) {
+      default:
+        llvm_unreachable("Bad type for urem");
+      // fallthrough
+      case IceType_i32:
+        break;
+      case IceType_i16:
+        Eax = Traits::RegisterSet::Reg_ax;
+        Edx = Traits::RegisterSet::Reg_dx;
+        break;
+      }
+      Constant *Zero = Ctx->getConstantZero(Ty);
+      T_edx = makeReg(Dest->getType(), Edx);
       _mov(T_edx, Zero);
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T, Src0, Eax);
       _div(T_edx, Src1, T);
       _mov(Dest, T_edx);
     }
     break;
   case InstArithmetic::Srem:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize mod by constant power of 2, but not for Om1 or O0, just to
       // keep things simple there.
@@ skipping 26 matching lines @@
           _add(T, Src0);
           _and(T, Ctx->getConstantInt(Ty, -(1 << LogDiv)));
           _sub(T, Src0);
           _neg(T);
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    if (isByteSizedArithType(Dest->getType())) {
-      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
-      // T is %al.
-      _cbwdq(T, T);
-      _idiv(T, Src1, T);
-      Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
-      Context.insert(InstFakeDef::create(Func, T_eax));
-      // shr $8, %eax shifts ah (i.e., the 8 bit remainder) into al. We don't
-      // mov %ah, %al because it would make x86-64 codegen more complicated. If
-      // this ever becomes a problem we can introduce a pseudo rem instruction
-      // that returns the remainder in %al directly (and uses a mov for copying
-      // %ah to %al.)
-      static constexpr uint8_t AlSizeInBits = 8;
-      _shr(T_eax, Ctx->getConstantInt8(AlSizeInBits));
-      _mov(Dest, T);
-      Context.insert(InstFakeUse::create(Func, T_eax));
-    } else {
-      T_edx = makeReg(Dest->getType(), Traits::RegisterSet::Reg_edx);
+    switch (Type Ty = Dest->getType()) {
+    default:
+      llvm_unreachable("Bad type for srem");
+    // fallthrough
+    case IceType_i32:
+      T_edx = makeReg(Ty, Traits::RegisterSet::Reg_edx);
       _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _cbwdq(T_edx, T);
       _idiv(T_edx, Src1, T);
       _mov(Dest, T_edx);
+      break;
+    case IceType_i16:
+      T_edx = makeReg(Ty, Traits::RegisterSet::Reg_dx);
+      _mov(T, Src0, Traits::RegisterSet::Reg_ax);
+      _cbwdq(T_edx, T);
+      _idiv(T_edx, Src1, T);
+      _mov(Dest, T_edx);
+      break;
+    case IceType_i8:
+      T_edx = makeReg(IceType_i16, Traits::RegisterSet::Reg_ax);
+      // TODO(stichnot): Use register ah for T_edx, and remove the _shr().
+      // T_edx = makeReg(Ty, Traits::RegisterSet::Reg_ah);
+      _mov(T, Src0, Traits::RegisterSet::Reg_al);
+      _cbwdq(T_edx, T);
+      _idiv(T_edx, Src1, T);
+      static constexpr uint8_t AlSizeInBits = 8;
+      _shr(T_edx, Ctx->getConstantInt8(AlSizeInBits));
+      _mov(Dest, T_edx);
+      break;
     }
     break;
   case InstArithmetic::Fadd:
     _mov(T, Src0);
     _addss(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Fsub:
     _mov(T, Src0);
     _subss(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Fmul:
     _mov(T, Src0);
     _mulss(T, Src0 == Src1 ? T : Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Fdiv:
     _mov(T, Src0);
     _divss(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Frem: {
-    const SizeT MaxSrcs = 2;
+    constexpr SizeT MaxSrcs = 2;
     Type Ty = Dest->getType();
     InstCall *Call = makeHelperCall(
         isFloat32Asserting32Or64(Ty) ? H_frem_f32 : H_frem_f64, Dest, MaxSrcs);
     Call->addArg(Src0);
     Call->addArg(Src1);
     return lowerCall(Call);
   }
   }
 }
 
@@ skipping 234 matching lines @@
     if (isVectorType(Dest->getType())) {
       assert(Dest->getType() == IceType_v4i32 &&
              Inst->getSrc(0)->getType() == IceType_v4f32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Tps2dq);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
-      const SizeT MaxSrcs = 1;
+      constexpr SizeT MaxSrcs = 1;
       Type SrcType = Inst->getSrc(0)->getType();
       InstCall *Call =
           makeHelperCall(isFloat32Asserting32Or64(SrcType) ? H_fptosi_f32_i64
                                                            : H_fptosi_f64_i64,
                          Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
     } else {
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
@@ skipping 10 matching lines @@
       _mov(T_2, T_1); // T_1 and T_2 may have different integer types
       if (Dest->getType() == IceType_i1)
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Fptoui:
     if (isVectorType(Dest->getType())) {
       assert(Dest->getType() == IceType_v4i32 &&
              Inst->getSrc(0)->getType() == IceType_v4f32);
-      const SizeT MaxSrcs = 1;
+      constexpr SizeT MaxSrcs = 1;
       InstCall *Call = makeHelperCall(H_fptoui_4xi32_f32, Dest, MaxSrcs);
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
     } else if (Dest->getType() == IceType_i64 ||
                (!Traits::Is64Bit && Dest->getType() == IceType_i32)) {
       // Use a helper for both x86-32 and x86-64.
-      const SizeT MaxSrcs = 1;
+      constexpr SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       Type SrcType = Inst->getSrc(0)->getType();
       IceString TargetString;
       if (Traits::Is64Bit) {
         TargetString = isFloat32Asserting32Or64(SrcType) ? H_fptoui_f32_i64
                                                          : H_fptoui_f64_i64;
       } else if (isInt32Asserting32Or64(DestType)) {
         TargetString = isFloat32Asserting32Or64(SrcType) ? H_fptoui_f32_i32
                                                          : H_fptoui_f64_i32;
       } else {
@@ skipping 28 matching lines @@
       assert(Dest->getType() == IceType_v4f32 &&
              Inst->getSrc(0)->getType() == IceType_v4i32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Dq2ps);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && Inst->getSrc(0)->getType() == IceType_i64) {
       // Use a helper for x86-32.
-      const SizeT MaxSrcs = 1;
+      constexpr SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       InstCall *Call =
           makeHelperCall(isFloat32Asserting32Or64(DestType) ? H_sitofp_i64_f32
                                                             : H_sitofp_i64_f64,
                          Dest, MaxSrcs);
       // TODO: Call the correct compiler-rt helper function.
       Call->addArg(Inst->getSrc(0));
       lowerCall(Call);
       return;
     } else {
@@ skipping 14 matching lines @@
         _movsx(T_1, Src0RM);
       _cvt(T_2, T_1, Traits::Insts::Cvt::Si2ss);
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Uitofp: {
     Operand *Src0 = Inst->getSrc(0);
     if (isVectorType(Src0->getType())) {
       assert(Dest->getType() == IceType_v4f32 &&
              Src0->getType() == IceType_v4i32);
-      const SizeT MaxSrcs = 1;
+      constexpr SizeT MaxSrcs = 1;
       InstCall *Call = makeHelperCall(H_uitofp_4xi32_4xf32, Dest, MaxSrcs);
       Call->addArg(Src0);
       lowerCall(Call);
     } else if (Src0->getType() == IceType_i64 ||
                (!Traits::Is64Bit && Src0->getType() == IceType_i32)) {
       // Use a helper for x86-32 and x86-64. Also use a helper for i32 on
       // x86-32.
-      const SizeT MaxSrcs = 1;
+      constexpr SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       IceString TargetString;
       if (isInt32Asserting32Or64(Src0->getType())) {
         TargetString = isFloat32Asserting32Or64(DestType) ? H_uitofp_i32_f32
                                                           : H_uitofp_i32_f64;
       } else {
         TargetString = isFloat32Asserting32Or64(DestType) ? H_uitofp_i64_f32
                                                           : H_uitofp_i64_f64;
       }
       InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs);
@@ skipping 195 matching lines @@
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(1));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
-  Variable *ExtractedElementR = makeReg(InVectorElementTy);
 
   // TODO(wala): Determine the best lowering sequences for each type.
   bool CanUsePextr = Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
-                     InstructionSet >= Traits::SSE4_1;
-  if (CanUsePextr && Ty != IceType_v4f32) {
-    // Use pextrb, pextrw, or pextrd.
+                     (InstructionSet >= Traits::SSE4_1 && Ty != IceType_v4f32);
+  Variable *ExtractedElementR =
+      makeReg(CanUsePextr ? IceType_i32 : InVectorElementTy);
+  if (CanUsePextr) {
+    // Use pextrb, pextrw, or pextrd.  The "b" and "w" versions clear the upper
+    // bits of the destination register, so we represent this by always
+    // extracting into an i32 register.  The _mov into Dest below will do
+    // truncation as necessary.
     Constant *Mask = Ctx->getConstantInt32(Index);
     Variable *SourceVectR = legalizeToReg(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
     Variable *T = nullptr;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted is not
       // at the lowest index.
       Constant *Mask = Ctx->getConstantInt32(Index);
@@ skipping 492 matching lines @@
     // Use insertps, pinsrb, pinsrw, or pinsrd.
     Operand *ElementRM =
         legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
     Variable *T = makeReg(Ty);
     _movp(T, SourceVectRM);
     if (Ty == IceType_v4f32)
       _insertps(T, ElementRM, Ctx->getConstantInt32(Index << 4));
     else
+      // TODO(stichnot): For the pinsrb and pinsrw instructions, when the source
+      // operand is a register, it must be a full r32 register like eax, and not
+      // ax/al/ah.  For filetype=asm, InstX86Pinsr<Machine>::emit() compensates
+      // for the use of r16 and r8 by converting them through getBaseReg(),
+      // while emitIAS() validates that the original and base register encodings
+      // are the same.  But for an "interior" register like ah, it should
+      // probably be copied into an r32 via movzx so that the types work out.
       _pinsr(T, ElementRM, Ctx->getConstantInt32(Index));
     _movp(Inst->getDest(), T);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use shufps or movss.
     Variable *ElementR = nullptr;
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
 
     if (InVectorElementTy == IceType_f32) {
       // ElementR will be in an XMM register since it is floating point.
@@ skipping 314 matching lines @@
     // well-defined value.
     Operand *Val = legalize(Instr->getArg(0));
     Operand *FirstVal;
     Operand *SecondVal = nullptr;
     if (!Traits::Is64Bit && Val->getType() == IceType_i64) {
       FirstVal = loOperand(Val);
       SecondVal = hiOperand(Val);
     } else {
       FirstVal = Val;
     }
-    const bool IsCttz = false;
+    constexpr bool IsCttz = false;
     lowerCountZeros(IsCttz, Val->getType(), Instr->getDest(), FirstVal,
                     SecondVal);
     return;
   }
   case Intrinsics::Cttz: {
     // The "is zero undef" parameter is ignored and we always return a
     // well-defined value.
     Operand *Val = legalize(Instr->getArg(0));
     Operand *FirstVal;
     Operand *SecondVal = nullptr;
     if (!Traits::Is64Bit && Val->getType() == IceType_i64) {
       FirstVal = hiOperand(Val);
       SecondVal = loOperand(Val);
     } else {
       FirstVal = Val;
     }
-    const bool IsCttz = true;
+    constexpr bool IsCttz = true;
     lowerCountZeros(IsCttz, Val->getType(), Instr->getDest(), FirstVal,
                     SecondVal);
     return;
   }
   case Intrinsics::Fabs: {
     Operand *Src = legalize(Instr->getArg(0));
     Type Ty = Src->getType();
     Variable *Dest = Instr->getDest();
     Variable *T = makeVectorOfFabsMask(Ty);
     // The pand instruction operates on an m128 memory operand, so if Src is an
@@ skipping 77 matching lines @@
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerAtomicCmpxchg(Variable *DestPrev,
                                                 Operand *Ptr, Operand *Expected,
                                                 Operand *Desired) {
-  if (!Traits::Is64Bit && Expected->getType() == IceType_i64) {
+  Type Ty = Expected->getType();
+  if (!Traits::Is64Bit && Ty == IceType_i64) {
     // Reserve the pre-colored registers first, before adding any more
     // infinite-weight variables from formMemoryOperand's legalization.
     Variable *T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
     Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
     Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
     Variable *T_ebx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ebx);
     _mov(T_eax, loOperand(Expected));
     _mov(T_edx, hiOperand(Expected));
     _mov(T_ebx, loOperand(Desired));
     _mov(T_ecx, hiOperand(Desired));
-    typename Traits::X86OperandMem *Addr =
-        formMemoryOperand(Ptr, Expected->getType());
-    const bool Locked = true;
+    typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
+    constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     Variable *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
-  Variable *T_eax = makeReg(Expected->getType(), Traits::RegisterSet::Reg_eax);
+  int32_t Eax;
+  switch (Ty) {
+  default:
+    llvm_unreachable("Bad type for cmpxchg");
+  // fallthrough
+  case IceType_i32:
+    Eax = Traits::RegisterSet::Reg_eax;
+    break;
+  case IceType_i16:
+    Eax = Traits::RegisterSet::Reg_ax;
+    break;
+  case IceType_i8:
+    Eax = Traits::RegisterSet::Reg_al;
+    break;
+  }
+  Variable *T_eax = makeReg(Ty, Eax);
   _mov(T_eax, Expected);
-  typename Traits::X86OperandMem *Addr =
-      formMemoryOperand(Ptr, Expected->getType());
+  typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
   Variable *DesiredReg = legalizeToReg(Desired);
-  const bool Locked = true;
+  constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 template <class Machine>
 bool TargetX86Base<Machine>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
                                                       Operand *PtrToMem,
                                                       Operand *Expected,
                                                       Operand *Desired) {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
@@ skipping 81 matching lines @@
     if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
       // All the fall-through paths must set this to true, but use this
       // for asserting.
       NeedsCmpxchg = true;
       Op_Lo = &TargetX86Base<Machine>::_add;
       Op_Hi = &TargetX86Base<Machine>::_adc;
       break;
     }
     typename Traits::X86OperandMem *Addr =
         formMemoryOperand(Ptr, Dest->getType());
-    const bool Locked = true;
+    constexpr bool Locked = true;
     Variable *T = nullptr;
     _mov(T, Val);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicSub: {
     if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
       Op_Lo = &TargetX86Base<Machine>::_sub;
       Op_Hi = &TargetX86Base<Machine>::_sbb;
       break;
     }
     typename Traits::X86OperandMem *Addr =
         formMemoryOperand(Ptr, Dest->getType());
-    const bool Locked = true;
+    constexpr bool Locked = true;
     Variable *T = nullptr;
     _mov(T, Val);
     _neg(T);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicOr:
     // TODO(jvoung): If Dest is null or dead, then some of these
     // operations do not need an "exchange", but just a locked op.
@@ skipping 87 matching lines @@
       _mov(T_ecx, T_edx);
       (this->*Op_Hi)(T_ecx, hiOperand(Val));
     } else {
       // This is for xchg, which doesn't need an actual Op_Lo/Op_Hi.
       // It just needs the Val loaded into ebx and ecx.
       // That can also be done before the loop.
       _mov(T_ebx, loOperand(Val));
       _mov(T_ecx, hiOperand(Val));
       Context.insert(Label);
     }
-    const bool Locked = true;
+    constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     _br(Traits::Cond::Br_ne, Label);
     if (!IsXchg8b) {
       // If Val is a variable, model the extended live range of Val through
       // the end of the loop, since it will be re-used by the loop.
       if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
         Variable *ValLo = llvm::cast<Variable>(loOperand(ValVar));
         Variable *ValHi = llvm::cast<Variable>(hiOperand(ValVar));
         Context.insert(InstFakeUse::create(Func, ValLo));
         Context.insert(InstFakeUse::create(Func, ValHi));
       }
     } else {
       // For xchg, the loop is slightly smaller and ebx/ecx are used.
       Context.insert(InstFakeUse::create(Func, T_ebx));
       Context.insert(InstFakeUse::create(Func, T_ecx));
     }
     // The address base (if any) is also reused in the loop.
     if (Variable *Base = Addr->getBase())
       Context.insert(InstFakeUse::create(Func, Base));
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
-  Variable *T_eax = makeReg(Ty, Traits::RegisterSet::Reg_eax);
+  int32_t Eax;
+  switch (Ty) {
+  default:
+    llvm_unreachable("Bad type for atomicRMW");
+  // fallthrough
+  case IceType_i32:
+    Eax = Traits::RegisterSet::Reg_eax;
+    break;
+  case IceType_i16:
+    Eax = Traits::RegisterSet::Reg_ax;
+    break;
+  case IceType_i8:
+    Eax = Traits::RegisterSet::Reg_al;
+    break;
+  }
+  Variable *T_eax = makeReg(Ty, Eax);
   _mov(T_eax, Addr);
   typename Traits::Insts::Label *Label =
       Traits::Insts::Label::create(Func, this);
   Context.insert(Label);
   // We want to pick a different register for T than Eax, so don't use
   // _mov(T == nullptr, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
-  const bool Locked = true;
+  constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
   _br(Traits::Cond::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
   if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
     Context.insert(InstFakeUse::create(Func, ValVar));
   }
   // The address base (if any) is also reused in the loop.
   if (Variable *Base = Addr->getBase())
     Context.insert(InstFakeUse::create(Func, Base));
@@ skipping 1357 matching lines @@
   assert(Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v8i16 ||
          Ty == IceType_v16i8);
   if (Ty == IceType_v4f32 || Ty == IceType_v4i32 || Ty == IceType_v8i16) {
     Variable *Reg = makeVectorOfOnes(Ty, RegNum);
     SizeT Shift =
         typeWidthInBytes(typeElementType(Ty)) * Traits::X86_CHAR_BIT - 1;
     _psll(Reg, Ctx->getConstantInt8(Shift));
     return Reg;
   } else {
     // SSE has no left shift operation for vectors of 8 bit integers.
-    const uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
+    constexpr uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
     Constant *ConstantMask = Ctx->getConstantInt32(HIGH_ORDER_BITS_MASK);
     Variable *Reg = makeReg(Ty, RegNum);
     _movd(Reg, legalize(ConstantMask, Legal_Reg | Legal_Mem));
     _pshufd(Reg, Reg, Ctx->getConstantZero(IceType_i8));
     return Reg;
   }
 }
 
 /// Construct a mask in a register that can be and'ed with a floating-point
 /// value to mask off its sign bit. The value will be <4 x 0x7fffffff> for f32
@@ skipping 13 matching lines @@
 typename TargetX86Base<Machine>::Traits::X86OperandMem *
 TargetX86Base<Machine>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
                                                      uint32_t Offset) {
   // Ensure that Loc is a stack slot.
   assert(Slot->mustNotHaveReg());
   assert(Slot->getRegNum() == Variable::NoRegister);
   // Compute the location of Loc in memory.
   // TODO(wala,stichnot): lea should not
   // be required. The address of the stack slot is known at compile time
   // (although not until after addProlog()).
-  const Type PointerType = IceType_i32;
+  constexpr Type PointerType = IceType_i32;
   Variable *Loc = makeReg(PointerType);
   _lea(Loc, Slot);
   Constant *ConstantOffset = Ctx->getConstantInt32(Offset);
   return Traits::X86OperandMem::create(Func, Ty, Loc, ConstantOffset);
 }
 
 /// Helper for legalize() to emit the right code to lower an operand to a
 /// register of the appropriate type.
 template <class Machine>
 Variable *TargetX86Base<Machine>::copyToReg(Operand *Src, int32_t RegNum) {
@@ skipping 32 matching lines @@
       if (Subst->mustHaveReg() && !Subst->hasReg()) {
         // At this point we know the substitution will have a register.
         if (From->getType() == Subst->getType()) {
           // At this point we know the substitution's register is compatible.
           return Subst;
         }
       }
     }
   }
 
-  if (auto Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(From)) {
+  if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure that the
     // Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
       RegBase = legalizeToReg(Base);
     }
     if (Index) {
@@ skipping 57 matching lines @@
       // Immediate specifically not allowed
       NeedsReg = true;
     if (!(Allowed & Legal_Mem) && isScalarFloatingType(Ty))
       // On x86, FP constants are lowered to mem operands.
       NeedsReg = true;
     if (NeedsReg) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
-  if (auto Var = llvm::dyn_cast<Variable>(From)) {
+  if (auto *Var = llvm::dyn_cast<Variable>(From)) {
     // Check if the variable is guaranteed a physical register. This can happen
     // either when the variable is pre-colored or when it is assigned infinite
     // weight.
     bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
@@ skipping 234 matching lines @@
       assert(Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool);
       Immediate->setShouldBePooled(true);
       // if we have already assigned a phy register, we must come from
       // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
       // assigned register as this assignment is that start of its use-def
       // chain. So we add RegNum argument here.
       Variable *Reg = makeReg(Immediate->getType(), RegNum);
       IceString Label;
       llvm::raw_string_ostream Label_stream(Label);
       Immediate->emitPoolLabel(Label_stream, Ctx);
-      const RelocOffsetT Offset = 0;
-      const bool SuppressMangling = true;
+      constexpr RelocOffsetT Offset = 0;
+      constexpr bool SuppressMangling = true;
       Constant *Symbol =
           Ctx->getConstantSym(Offset, Label_stream.str(), SuppressMangling);
       typename Traits::X86OperandMem *MemOperand =
           Traits::X86OperandMem::create(Func, Immediate->getType(), nullptr,
                                         Symbol);
       _mov(Reg, MemOperand);
       return Reg;
     }
     assert("Unsupported -randomize-pool-immediates option" && false);
   }
@@ skipping 75 matching lines @@
         // phi lowering, we should not ask for new physical registers in
         // general. However, if we do meet Memory Operand during phi lowering,
         // we should not blind or pool the immediates for now.
         if (RegNum != Variable::NoRegister)
           return MemOperand;
         Variable *RegTemp = makeReg(IceType_i32);
         IceString Label;
         llvm::raw_string_ostream Label_stream(Label);
         MemOperand->getOffset()->emitPoolLabel(Label_stream, Ctx);
         MemOperand->getOffset()->setShouldBePooled(true);
-        const RelocOffsetT SymOffset = 0;
-        bool SuppressMangling = true;
+        constexpr RelocOffsetT SymOffset = 0;
+        constexpr bool SuppressMangling = true;
         Constant *Symbol = Ctx->getConstantSym(SymOffset, Label_stream.str(),
                                                SuppressMangling);
         typename Traits::X86OperandMem *SymbolOperand =
             Traits::X86OperandMem::create(
                 Func, MemOperand->getOffset()->getType(), nullptr, Symbol);
         _mov(RegTemp, SymbolOperand);
         // If we have a base variable here, we should add the lea instruction
         // to add the value of the base variable to RegTemp. If there is no
         // base variable, we won't need this lea instruction.
         if (MemOperand->getBase()) {
@@ skipping 15 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H