Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 43 matching lines @@
   static constexpr bool HasPopa = false;
   static constexpr bool HasPusha = false;
   static constexpr bool UsesX87 = false;
   static constexpr ::Ice::RegX8664::GPRRegister Last8BitGPR =
       ::Ice::RegX8664::GPRRegister::Encoded_Reg_r15d;
 
   enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 };
 
   using GPRRegister = ::Ice::RegX8664::GPRRegister;
   using XmmRegister = ::Ice::RegX8664::XmmRegister;
-  using ByteRegister = ::Ice::RegX8664::ByteRegister;
 
   using Cond = ::Ice::CondX8664;
 
   using RegisterSet = ::Ice::RegX8664;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
   static const FixupKind PcRelFixup = llvm::ELF::R_X86_64_PC32;
   static const FixupKind RelFixup = llvm::ELF::R_X86_64_32S;
 
   class Operand {
@@ skipping 216 matching lines @@
     Begin,
     // SSE2 is the PNaCl baseline instruction set.
     SSE2 = Begin,
     SSE4_1,
     End
   };
 
   static const char *TargetName;
   static constexpr Type WordType = IceType_i64;
 
-  static IceString getRegName(SizeT RegNum, Type Ty) {
-    assert(RegNum < RegisterSet::Reg_NUM);
-    static const struct {
-      const char *const Name8;
-      const char *const Name16;
-      const char *const Name /*32*/;
-      const char *const Name64;
-    } RegNames[] = {
-#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
-          stackptr, frameptr, isInt, isFP)                                     \
-  { name8, name16, name32, name64 }                                            \
-  ,
+  static IceString getRegName(int32_t RegNum) {
+    static const char *const RegNames[] = {
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+  name,
         REGX8664_TABLE
 #undef X
     };
+    assert(RegNum >= 0);
+    assert(RegNum < RegisterSet::Reg_NUM);
+    return RegNames[RegNum];
+  }
 
-    switch (Ty) {
-    case IceType_i1:
-    case IceType_i8:
-      return RegNames[RegNum].Name8;
-    case IceType_i16:
-      return RegNames[RegNum].Name16;
-    case IceType_i64:
-      return RegNames[RegNum].Name64;
-    default:
-      return RegNames[RegNum].Name;
-    }
+  static GPRRegister getEncodedGPR(int32_t RegNum) {
+    static const GPRRegister GPRRegs[] = {
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+  GPRRegister(isGPR ? encode : GPRRegister::Encoded_Not_GPR),
+        REGX8664_TABLE
+#undef X
+    };
+    assert(RegNum >= 0);
+    assert(RegNum < RegisterSet::Reg_NUM);
+    assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR);
+    return GPRRegs[RegNum];
   }
 
+  static XmmRegister getEncodedXmm(int32_t RegNum) {
+    static const XmmRegister XmmRegs[] = {
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+  XmmRegister(isXmm ? encode : XmmRegister::Encoded_Not_Xmm),
+        REGX8664_TABLE
+#undef X
+    };
+    assert(RegNum >= 0);
+    assert(RegNum < RegisterSet::Reg_NUM);
+    assert(XmmRegs[RegNum] != XmmRegister::Encoded_Not_Xmm);
+    return XmmRegs[RegNum];
+  }
+
+  static uint32_t getEncoding(int32_t RegNum) {
+    static const uint32_t Encoding[] = {
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+  encode,
+        REGX8664_TABLE
+#undef X
+    };
+    assert(RegNum >= 0);
+    assert(RegNum < RegisterSet::Reg_NUM);
+    return Encoding[RegNum];
+  }
+
+  static inline int32_t getBaseReg(int32_t RegNum) {
+    static const int32_t BaseRegs[] = {
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+  RegisterSet::base,
+        REGX8664_TABLE
+#undef X
+    };
+    assert(RegNum >= 0);
+    assert(RegNum < RegisterSet::Reg_NUM);
+    return BaseRegs[RegNum];
+  }
+
+  static int32_t getGprForType(Type, int32_t RegNum) { return RegNum; }
+
   static void initRegisterSet(
       std::array<llvm::SmallBitVector, IceType_NUM> *TypeToRegisterSet,
       std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases,
       llvm::SmallBitVector *ScratchRegs) {
-    llvm::SmallBitVector IntegerRegisters(RegisterSet::Reg_NUM);
+    llvm::SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM);
+    llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM);
+    llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM);
     llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
     llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM);
     ScratchRegs->resize(RegisterSet::Reg_NUM);
 
-#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
-          stackptr, frameptr, isInt, isFP)                                     \
-  (IntegerRegisters)[RegisterSet::val] = isInt;                                \
-  (IntegerRegistersI8)[RegisterSet::val] = isInt;                              \
-  (FloatRegisters)[RegisterSet::val] = isFP;                                   \
-  (VectorRegisters)[RegisterSet::val] = isFP;                                  \
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+  (IntegerRegistersI64)[RegisterSet::val] = is64;                              \
+  (IntegerRegistersI32)[RegisterSet::val] = is32;                              \
+  (IntegerRegistersI16)[RegisterSet::val] = is16;                              \
+  (IntegerRegistersI8)[RegisterSet::val] = is8;                                \
+  (FloatRegisters)[RegisterSet::val] = isXmm;                                  \
+  (VectorRegisters)[RegisterSet::val] = isXmm;                                 \
   (*RegisterAliases)[RegisterSet::val].resize(RegisterSet::Reg_NUM);           \
+  for (SizeT RegAlias : aliases) {                                             \
+    assert(!(*RegisterAliases)[RegisterSet::val][RegAlias] &&                  \
+           "Duplicate alias for " #val);                                       \
+    (*RegisterAliases)[RegisterSet::val].set(RegAlias);                        \
+  }                                                                            \
   (*RegisterAliases)[RegisterSet::val].set(RegisterSet::val);                  \
   (*ScratchRegs)[RegisterSet::val] = scratch;
     REGX8664_TABLE;
 #undef X
 
     (*TypeToRegisterSet)[IceType_void] = InvalidRegisters;
     (*TypeToRegisterSet)[IceType_i1] = IntegerRegistersI8;
     (*TypeToRegisterSet)[IceType_i8] = IntegerRegistersI8;
-    (*TypeToRegisterSet)[IceType_i16] = IntegerRegisters;
-    (*TypeToRegisterSet)[IceType_i32] = IntegerRegisters;
-    (*TypeToRegisterSet)[IceType_i64] = IntegerRegisters;
+    (*TypeToRegisterSet)[IceType_i16] = IntegerRegistersI16;
+    (*TypeToRegisterSet)[IceType_i32] = IntegerRegistersI32;
+    (*TypeToRegisterSet)[IceType_i64] = IntegerRegistersI64;
     (*TypeToRegisterSet)[IceType_f32] = FloatRegisters;
     (*TypeToRegisterSet)[IceType_f64] = FloatRegisters;
     (*TypeToRegisterSet)[IceType_v4i1] = VectorRegisters;
     (*TypeToRegisterSet)[IceType_v8i1] = VectorRegisters;
     (*TypeToRegisterSet)[IceType_v16i1] = VectorRegisters;
     (*TypeToRegisterSet)[IceType_v16i8] = VectorRegisters;
     (*TypeToRegisterSet)[IceType_v8i16] = VectorRegisters;
     (*TypeToRegisterSet)[IceType_v4i32] = VectorRegisters;
     (*TypeToRegisterSet)[IceType_v4f32] = VectorRegisters;
   }
 
   static llvm::SmallBitVector
   getRegisterSet(TargetLowering::RegSetMask Include,
                  TargetLowering::RegSetMask Exclude) {
     llvm::SmallBitVector Registers(RegisterSet::Reg_NUM);
 
-#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
-          stackptr, frameptr, isInt, isFP)                                     \
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
   if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave))         \
     Registers[RegisterSet::val] = true;                                        \
   if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave))       \
     Registers[RegisterSet::val] = true;                                        \
   if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer))      \
     Registers[RegisterSet::val] = true;                                        \
   if (frameptr && (Include & ::Ice::TargetLowering::RegSet_FramePointer))      \
     Registers[RegisterSet::val] = true;                                        \
   if (scratch && (Exclude & ::Ice::TargetLowering::RegSet_CallerSave))         \
     Registers[RegisterSet::val] = false;                                       \
@@ skipping 24 matching lines @@
     // for performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>;
     using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
     EquivalenceClassMap EquivalenceClasses;
     SizeT NumShuffled = 0, NumPreserved = 0;
 
 // Build up the equivalence classes of registers by looking at the register
 // properties as well as whether the registers should be explicitly excluded
 // from shuffling.
-#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
-          stackptr, frameptr, isInt, isFP)                                     \
+#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
+          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
+          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
   if (ExcludeRegisters[RegisterSet::val]) {                                    \
     /* val stays the same in the resulting permutation. */                     \
     Permutation[RegisterSet::val] = RegisterSet::val;                          \
     ++NumPreserved;                                                            \
   } else {                                                                     \
-    const uint32_t Index = (scratch << 0) | (preserved << 1) |                 \
-                           (/*isI8=*/1 << 2) | (isInt << 3) | (isFP << 4);     \
+    const uint32_t Index = (scratch << 0) | (preserved << 1) | (is8 << 2) |    \

[Karl, 2015/10/27 16:13:19]

There appears to be patterns in these shifts (is8 << 2) etc.  Should the 2 be a
constexpr is8 << is8Shift?

[Jim Stichnoth, 2015/10/27 19:14:09]

The purpose here was to combine the relevant attributes of the register into a
single value that is used to identify its equivalence class.  I think it's
easier to convey this using the obviously unique constants, rather than using
symbolic constants that aren't obviously unique (unless you look back to their
definitions).

That said, I restructured this so that it conveys the intent without using magic
constants.

+                           (is16 << 3) | (is32 << 4) | (is64 << 5) |           \
+                           (isXmm << 6);                                       \
     /* val is assigned to an equivalence class based on its properties. */     \
     EquivalenceClasses[Index].push_back(RegisterSet::val);                     \
   }
     REGX8664_TABLE
 #undef X
 
     // Create a random number generator for regalloc randomization.
     RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(),
                               RPE_RegAllocRandomization, Salt);
     RandomNumberGeneratorWrapper RNGW(RNG);
@@ skipping 16 matching lines @@
       Ostream &Str = Func->getContext()->getStrDump();
       Str << "Register equivalence classes:\n";
       for (auto I : EquivalenceClasses) {
         Str << "{";
         const RegisterList &List = I.second;
         bool First = true;
         for (int32_t Register : List) {
           if (!First)
             Str << " ";
           First = false;
-          Str << getRegName(Register, IceType_i32);
+          Str << getRegName(Register);
         }
         Str << "}\n";
       }
     }
   }
 
   /// The maximum number of arguments to pass in XMM registers
   static const uint32_t X86_MAX_XMM_ARGS = 8;
   /// The maximum number of arguments to pass in GPR registers
   static const uint32_t X86_MAX_GPR_ARGS = 6;
@@ skipping 271 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8664 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H