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Side by Side Diff: src/IceInstX8632.def

Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Add some comments Created 5 years, 1 month ago
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1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-32 instructions in the 10 // This file defines properties of lowered x86-32 instructions in the
11 // form of x-macros. 11 // form of x-macros.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF 15 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF
16 #define SUBZERO_SRC_ICEINSTX8632_DEF 16 #define SUBZERO_SRC_ICEINSTX8632_DEF
17 17
18 // NOTE: esp is not considered isInt, to avoid register allocating it. 18 #include "IceRegList.h"
19 #define REGX8632_GPR_TABLE \ 19
20 /* val, encode, name, name16, name8, scratch, preserved, stackptr, \ 20 // x86-32 ABI:
21 frameptr, isI8, isInt, isFP */ \ 21 // Scratch GPRs: eax, ecx, edx
22 X(Reg_eax, 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \ 22 // Callee-save GPRs: ebx, ebp, esi, edi
23 X(Reg_ecx, 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \ 23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
24 X(Reg_edx, 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \ 24 // Key to table columns:
25 X(Reg_ebx, 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \ 25 // val: Enum value, when a specific register is needed during lowering.
26 X(Reg_esp, 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 0, 0) \ 26 // encode: Encoding in the integrated assembler.
27 X(Reg_ebp, 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \ 27 // name: Name used for the external assembler.
28 X(Reg_esi, 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \ 28 // scratch: Scratch (caller-save) register.
29 X(Reg_edi, 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0) 29 // preserved: Preserved (callee-save) register.
30 30 // stackptr: This register is used as the stack pointer.
31 #define REGX8632_XMM_TABLE \ 31 // frameptr: This register is used as the frame pointer if needed.
32 X(Reg_xmm0, 0, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 32 // isGPR: This is a GPR (integer-type).
33 X(Reg_xmm1, 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 33 // is64: This is a 64-bit GPR.
34 X(Reg_xmm2, 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 34 // is32: This is a 32-bit GPR.
35 X(Reg_xmm3, 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 35 // is16: This is a 16-bit GPR.
36 X(Reg_xmm4, 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 36 // is8: This is an 8-bit GPR.
37 X(Reg_xmm5, 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 37 // isXmm: This is an XMM register for FP and vector ops.
38 X(Reg_xmm6, 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 38 // is64To8: A 64-bit GPR truncable to 8-bit.
39 X(Reg_xmm7, 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 39 // is32To8: A 32-bit GPR truncable to 8-bit.
40 //#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, 40 // is16To8: A 16-bit GPR truncable to 8-bit.
41 // frameptr, isI8, isInt, isFP) 41 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
42 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
43 // aliases: List of register aliases, which need not include this register.
44 #define REGX8632_GPR_TABLE \
45 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
46 isGPR,is64,is32,is16,is8, isXmm, \
47 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
48 /* 32-bit registers */ \
49 X(Reg_eax, 0, "eax", Reg_eax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
50 REGLIST3(RegX8632, ax, al, ah)) \
51 X(Reg_ecx, 1, "ecx", Reg_ecx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
52 REGLIST3(RegX8632, cx, cl, ch)) \
53 X(Reg_edx, 2, "edx", Reg_edx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
54 REGLIST3(RegX8632, dx, dl, dh)) \
55 X(Reg_ebx, 3, "ebx", Reg_ebx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
56 REGLIST3(RegX8632, bx, bl, bh)) \
57 X(Reg_esp, 4, "esp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
58 REGLIST1(RegX8632, sp)) \
59 X(Reg_ebp, 5, "ebp", Reg_ebp, 0,1,0,1, 1,0,1,0,0, 0, 0,0,0,0,0, \
60 REGLIST1(RegX8632, bp)) \
61 X(Reg_esi, 6, "esi", Reg_esi, 0,1,0,0, 1,0,1,0,0, 0, 0,0,0,0,0, \
62 REGLIST1(RegX8632, si)) \
63 X(Reg_edi, 7, "edi", Reg_edi, 0,1,0,0, 1,0,1,0,0, 0, 0,0,0,0,0, \
64 REGLIST1(RegX8632, di)) \
65 /* 16-bit registers */ \
66 X(Reg_ax, 0, "ax", Reg_eax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
67 REGLIST3(RegX8632, eax, al, ah)) \
68 X(Reg_cx, 1, "cx", Reg_ecx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
69 REGLIST3(RegX8632, ecx, cl, ch)) \
70 X(Reg_dx, 2, "dx", Reg_edx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
71 REGLIST3(RegX8632, edx, dl, dh)) \
72 X(Reg_bx, 3, "bx", Reg_ebx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
73 REGLIST3(RegX8632, ebx, bl, bh)) \
74 X(Reg_sp, 4, "sp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
75 REGLIST1(RegX8632, esp)) \
76 X(Reg_bp, 5, "bp", Reg_ebp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,0,0,0, \
77 REGLIST1(RegX8632, ebp)) \
78 X(Reg_si, 6, "si", Reg_esi, 0,1,0,0, 1,0,0,1,0, 0, 0,0,0,0,0, \
79 REGLIST1(RegX8632, esi)) \
80 X(Reg_di, 7, "di", Reg_edi, 0,1,0,0, 1,0,0,1,0, 0, 0,0,0,0,0, \
81 REGLIST1(RegX8632, edi)) \
82 /* 8-bit registers */ \
83 X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
84 REGLIST2(RegX8632, eax, ax)) \
85 X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
86 REGLIST2(RegX8632, ecx, cx)) \
87 X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
88 REGLIST2(RegX8632, edx, dx)) \
89 X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
90 REGLIST2(RegX8632, ebx, bx)) \
91 /* High 8-bit registers */ \
92 X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
93 REGLIST2(RegX8632, eax, ax)) \
94 X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
95 REGLIST2(RegX8632, ecx, cx)) \
96 X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
97 REGLIST2(RegX8632, edx, dx)) \
98 X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
99 REGLIST2(RegX8632, ebx, bx)) \
100 /* End of GPR register set */
101 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
102 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
103 // isTrunc8Rcvr, isAhRcvr, aliases)
104
105 // Note: It would be more appropriate to list the xmm register aliases as
106 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so
107 // we use REGLIST1() to redundantly assign the register itself as an alias.
108 #define REGX8632_XMM_TABLE \
109 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
110 isGPR,is64,is32,is16,is8, isXmm, \
111 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
112 /* xmm registers */ \
113 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
114 REGLIST1(RegX8632, xmm0)) \
115 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
116 REGLIST1(RegX8632, xmm1)) \
117 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
118 REGLIST1(RegX8632, xmm2)) \
119 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
120 REGLIST1(RegX8632, xmm3)) \
121 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
122 REGLIST1(RegX8632, xmm4)) \
123 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
124 REGLIST1(RegX8632, xmm5)) \
125 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
126 REGLIST1(RegX8632, xmm6)) \
127 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
128 REGLIST1(RegX8632, xmm7)) \
129 /* End of xmm register set */
130 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
131 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
132 // isTrunc8Rcvr, isAhRcvr, aliases)
42 133
43 // We also provide a combined table, so that there is a namespace where 134 // We also provide a combined table, so that there is a namespace where
44 // all of the registers are considered and have distinct numberings. 135 // all of the registers are considered and have distinct numberings.
45 // This is in contrast to the above, where the "encode" is based on how 136 // This is in contrast to the above, where the "encode" is based on how
46 // the register numbers will be encoded in binaries and values can overlap. 137 // the register numbers will be encoded in binaries and values can overlap.
47 #define REGX8632_TABLE \ 138 #define REGX8632_TABLE \
48 /* val, encode, name, name16, name8, scratch, preserved, stackptr, \ 139 REGX8632_GPR_TABLE \
49 frameptr, isI8, isInt, isFP */ \
50 REGX8632_GPR_TABLE \
51 REGX8632_XMM_TABLE 140 REGX8632_XMM_TABLE
52 //#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, 141 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
53 // frameptr, isI8, isInt, isFP) 142 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
54 143 // isTrunc8Rcvr, isAhRcvr, aliases)
55 #define REGX8632_TABLE_BOUNDS \
56 /* val, init */ \
57 X(Reg_GPR_First, = Reg_eax) \
58 X(Reg_GPR_Last, = Reg_edi) \
59 X(Reg_XMM_First, = Reg_xmm0) \
60 X(Reg_XMM_Last, = Reg_xmm7) \
61 //define X(val, init)
62
63 // We also need the encodings for the Byte registers (other info overlaps
64 // what is in the REGX8632_GPR_TABLE).
65 #define REGX8632_BYTEREG_TABLE \
66 /* val, encode */ \
67 X(Reg_al, = 0) \
68 X(Reg_cl, = 1) \
69 X(Reg_dl, = 2) \
70 X(Reg_bl, = 3)
71 //#define X(val, encode)
72 144
73 // X86 segment registers. 145 // X86 segment registers.
74 #define SEG_REGX8632_TABLE \ 146 #define SEG_REGX8632_TABLE \
75 /* enum value, name, prefix */ \ 147 /* val, name, prefix */ \
76 X(SegReg_CS, "cs", 0x2E) \ 148 X(SegReg_CS, "cs", 0x2E) \
77 X(SegReg_DS, "ds", 0x3E) \ 149 X(SegReg_DS, "ds", 0x3E) \
78 X(SegReg_ES, "es", 0x26) \ 150 X(SegReg_ES, "es", 0x26) \
79 X(SegReg_SS, "ss", 0x36) \ 151 X(SegReg_SS, "ss", 0x36) \
80 X(SegReg_FS, "fs", 0x64) \ 152 X(SegReg_FS, "fs", 0x64) \
81 X(SegReg_GS, "gs", 0x65) \ 153 X(SegReg_GS, "gs", 0x65)
82 //#define X(val, name, prefix) 154 //#define X(val, name, prefix)
83 155
84 // X87 ST(n) registers. 156 // X87 ST(n) registers.
85 #define X87ST_REGX8632_TABLE \ 157 #define X87ST_REGX8632_TABLE \
86 /* enum value, encode, name */ \ 158 /* val, encode, name */ \
87 X(X87ST_First, = 0, "st(0)") \ 159 X(X87ST_First, 0, "st(0)") \
88 X(X87ST_0, = 0, "st(0)") \ 160 X(X87ST_0, 0, "st(0)") \
89 X(X87ST_1, = 1, "st(1)") \ 161 X(X87ST_1, 1, "st(1)") \
90 X(X87ST_2, = 2, "st(2)") \ 162 X(X87ST_2, 2, "st(2)") \
91 X(X87ST_3, = 3, "st(3)") \ 163 X(X87ST_3, 3, "st(3)") \
92 X(X87ST_4, = 4, "st(4)") \ 164 X(X87ST_4, 4, "st(4)") \
93 X(X87ST_5, = 5, "st(5)") \ 165 X(X87ST_5, 5, "st(5)") \
94 X(X87ST_6, = 6, "st(6)") \ 166 X(X87ST_6, 6, "st(6)") \
95 X(X87ST_7, = 7, "st(7)") \ 167 X(X87ST_7, 7, "st(7)") \
96 X(X87ST_Last, = 7, "st(7)") \ 168 X(X87ST_Last, 7, "st(7)")
97 //#define X(val, encode, name) 169 //#define X(val, encode, name)
98 170
99 #define ICEINSTX8632BR_TABLE \ 171 #define ICEINSTX8632BR_TABLE \
100 /* enum value, encode, opposite, dump, emit */ \ 172 /* val, encode, opposite, dump, emit */ \
101 X(Br_o, = 0, Br_no, "o", "jo") \ 173 X(Br_o, 0, Br_no, "o", "jo") \
102 X(Br_no, = 1, Br_o, "no", "jno") \ 174 X(Br_no, 1, Br_o, "no", "jno") \
103 X(Br_b, = 2, Br_ae, "b", "jb") \ 175 X(Br_b, 2, Br_ae, "b", "jb") \
104 X(Br_ae, = 3, Br_b, "ae", "jae") \ 176 X(Br_ae, 3, Br_b, "ae", "jae") \
105 X(Br_e, = 4, Br_ne, "e", "je") \ 177 X(Br_e, 4, Br_ne, "e", "je") \
106 X(Br_ne, = 5, Br_e, "ne", "jne") \ 178 X(Br_ne, 5, Br_e, "ne", "jne") \
107 X(Br_be, = 6, Br_a, "be", "jbe") \ 179 X(Br_be, 6, Br_a, "be", "jbe") \
108 X(Br_a, = 7, Br_be, "a", "ja") \ 180 X(Br_a, 7, Br_be, "a", "ja") \
109 X(Br_s, = 8, Br_ns, "s", "js") \ 181 X(Br_s, 8, Br_ns, "s", "js") \
110 X(Br_ns, = 9, Br_s, "ns", "jns") \ 182 X(Br_ns, 9, Br_s, "ns", "jns") \
111 X(Br_p, = 10, Br_np, "p", "jp") \ 183 X(Br_p, 10, Br_np, "p", "jp") \
112 X(Br_np, = 11, Br_p, "np", "jnp") \ 184 X(Br_np, 11, Br_p, "np", "jnp") \
113 X(Br_l, = 12, Br_ge, "l", "jl") \ 185 X(Br_l, 12, Br_ge, "l", "jl") \
114 X(Br_ge, = 13, Br_l, "ge", "jge") \ 186 X(Br_ge, 13, Br_l, "ge", "jge") \
115 X(Br_le, = 14, Br_g, "le", "jle") \ 187 X(Br_le, 14, Br_g, "le", "jle") \
116 X(Br_g, = 15, Br_le, "g", "jg") \ 188 X(Br_g, 15, Br_le, "g", "jg")
117 //#define X(tag, encode, opp, dump, emit) 189 //#define X(val, encode, opp, dump, emit)
118 190
119 #define ICEINSTX8632CMPPS_TABLE \ 191 #define ICEINSTX8632CMPPS_TABLE \
120 /* enum value, emit */ \ 192 /* val, emit */ \
121 X(Cmpps_eq, "eq") \ 193 X(Cmpps_eq, "eq") \
122 X(Cmpps_lt, "lt") \ 194 X(Cmpps_lt, "lt") \
123 X(Cmpps_le, "le") \ 195 X(Cmpps_le, "le") \
124 X(Cmpps_unord, "unord") \ 196 X(Cmpps_unord, "unord") \
125 X(Cmpps_neq, "neq") \ 197 X(Cmpps_neq, "neq") \
126 X(Cmpps_nlt, "nlt") \ 198 X(Cmpps_nlt, "nlt") \
127 X(Cmpps_nle, "nle") \ 199 X(Cmpps_nle, "nle") \
128 X(Cmpps_ord, "ord") \ 200 X(Cmpps_ord, "ord")
129 //#define X(tag, emit) 201 //#define X(val, emit)
130 202
131 #define ICETYPEX8632_TABLE \ 203 #define ICETYPEX8632_TABLE \
132 /* tag, element type, cvt, sdss, pack, width, fld */ \ 204 /* tag, element type, cvt , sdss, pack, width, fld */ \
133 X(IceType_void, IceType_void, "?" , "" , "" , "", "") \ 205 X(IceType_void, IceType_void, "?", "", "", "", "") \
134 X(IceType_i1, IceType_void, "si", "" , "" , "b", "") \ 206 X(IceType_i1, IceType_void, "si", "", "", "b", "") \
135 X(IceType_i8, IceType_void, "si", "" , "" , "b", "") \ 207 X(IceType_i8, IceType_void, "si", "", "", "b", "") \
136 X(IceType_i16, IceType_void, "si", "" , "" , "w", "") \ 208 X(IceType_i16, IceType_void, "si", "", "", "w", "") \
137 X(IceType_i32, IceType_void, "si", "" , "" , "l", "") \ 209 X(IceType_i32, IceType_void, "si", "", "", "l", "") \
138 X(IceType_i64, IceType_void, "si", "" , "" , "q", "") \ 210 X(IceType_i64, IceType_void, "si", "", "", "q", "") \
139 X(IceType_f32, IceType_void, "ss", "ss", "d", "", "s") \ 211 X(IceType_f32, IceType_void, "ss", "ss", "d", "", "s") \
140 X(IceType_f64, IceType_void, "sd", "sd", "q", "", "l") \ 212 X(IceType_f64, IceType_void, "sd", "sd", "q", "", "l") \
141 X(IceType_v4i1, IceType_i32 , "?" , "" , "d", "", "") \ 213 X(IceType_v4i1, IceType_i32, "?", "", "d", "", "") \
142 X(IceType_v8i1, IceType_i16 , "?" , "" , "w", "", "") \ 214 X(IceType_v8i1, IceType_i16, "?", "", "w", "", "") \
143 X(IceType_v16i1, IceType_i8 , "?" , "" , "b", "", "") \ 215 X(IceType_v16i1, IceType_i8, "?", "", "b", "", "") \
144 X(IceType_v16i8, IceType_i8 , "?" , "" , "b", "", "") \ 216 X(IceType_v16i8, IceType_i8, "?", "", "b", "", "") \
145 X(IceType_v8i16, IceType_i16 , "?" , "" , "w", "", "") \ 217 X(IceType_v8i16, IceType_i16, "?", "", "w", "", "") \
146 X(IceType_v4i32, IceType_i32 , "dq", "" , "d", "", "") \ 218 X(IceType_v4i32, IceType_i32, "dq", "", "d", "", "") \
147 X(IceType_v4f32, IceType_f32 , "ps", "" , "d", "", "") \ 219 X(IceType_v4f32, IceType_f32, "ps", "", "d", "", "")
148 //#define X(tag, elementty, cvt, sdss, pack, width, fld) 220 //#define X(tag, elementty, cvt, sdss, pack, width, fld)
149 221
150 #endif // SUBZERO_SRC_ICEINSTX8632_DEF 222 #endif // SUBZERO_SRC_ICEINSTX8632_DEF
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