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Side by Side Diff: src/IceAssemblerX86BaseImpl.h

Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Add some comments Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=//
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
3 // for details. All rights reserved. Use of this source code is governed by a 3 // for details. All rights reserved. Use of this source code is governed by a
4 // BSD-style license that can be found in the LICENSE file. 4 // BSD-style license that can be found in the LICENSE file.
5 // 5 //
6 // Modified by the Subzero authors. 6 // Modified by the Subzero authors.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // The Subzero Code Generator 10 // The Subzero Code Generator
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170 170
171 template <class Machine> 171 template <class Machine>
172 template <typename, typename> 172 template <typename, typename>
173 void AssemblerX86Base<Machine>::popal() { 173 void AssemblerX86Base<Machine>::popal() {
174 AssemblerBuffer::EnsureCapacity ensured(&Buffer); 174 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
175 emitUint8(0x61); 175 emitUint8(0x61);
176 } 176 }
177 177
178 template <class Machine> 178 template <class Machine>
179 void AssemblerX86Base<Machine>::setcc(typename Traits::Cond::BrCond condition, 179 void AssemblerX86Base<Machine>::setcc(typename Traits::Cond::BrCond condition,
180 typename Traits::ByteRegister dst) { 180 typename Traits::GPRRegister dst) {
181 AssemblerBuffer::EnsureCapacity ensured(&Buffer); 181 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
182 emitRexB(IceType_i8, dst); 182 emitRexB(IceType_i8, dst);
183 emitUint8(0x0F); 183 emitUint8(0x0F);
184 emitUint8(0x90 + condition); 184 emitUint8(0x90 + condition);
185 emitUint8(0xC0 + gprEncoding(dst)); 185 emitUint8(0xC0 + gprEncoding(dst));
186 } 186 }
187 187
188 template <class Machine> 188 template <class Machine>
189 void AssemblerX86Base<Machine>::setcc(typename Traits::Cond::BrCond condition, 189 void AssemblerX86Base<Machine>::setcc(typename Traits::Cond::BrCond condition,
190 const typename Traits::Address &address) { 190 const typename Traits::Address &address) {
(...skipping 3245 matching lines...) Expand 10 before | Expand all | Expand 10 after
3436 (void)shifter; 3436 (void)shifter;
3437 if (Ty == IceType_i16) 3437 if (Ty == IceType_i16)
3438 emitOperandSizeOverride(); 3438 emitOperandSizeOverride();
3439 emitRexB(Ty, operand.rm()); 3439 emitRexB(Ty, operand.rm());
3440 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); 3440 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3);
3441 emitOperand(rm, operand); 3441 emitOperand(rm, operand);
3442 } 3442 }
3443 3443
3444 } // end of namespace X86Internal 3444 } // end of namespace X86Internal
3445 } // end of namespace Ice 3445 } // end of namespace Ice
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