Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(60)

Side by Side Diff: src/mips/assembler-mips.h

Issue 1419753008: MIPS: [turbofan] Properly implement Float64/32 Min/Max instructions. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Remove redundant functions. Created 5 years, 1 month ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/compiler/mips64/instruction-selector-mips64.cc ('k') | src/mips64/assembler-mips64.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 791 matching lines...) Expand 10 before | Expand all | Expand 10 after
802 void selnez(Register rd, Register rs, Register rt); 802 void selnez(Register rd, Register rs, Register rt);
803 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, 803 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs,
804 FPURegister ft); 804 FPURegister ft);
805 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); 805 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft);
806 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); 806 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft);
807 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); 807 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft);
808 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); 808 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft);
809 809
810 void movz_s(FPURegister fd, FPURegister fs, Register rt); 810 void movz_s(FPURegister fd, FPURegister fs, Register rt);
811 void movz_d(FPURegister fd, FPURegister fs, Register rt); 811 void movz_d(FPURegister fd, FPURegister fs, Register rt);
812 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc); 812 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0);
813 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc); 813 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0);
814 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc); 814 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0);
815 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc); 815 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0);
816 void movn_s(FPURegister fd, FPURegister fs, Register rt); 816 void movn_s(FPURegister fd, FPURegister fs, Register rt);
817 void movn_d(FPURegister fd, FPURegister fs, Register rt); 817 void movn_d(FPURegister fd, FPURegister fs, Register rt);
818 // Bit twiddling. 818 // Bit twiddling.
819 void clz(Register rd, Register rs); 819 void clz(Register rd, Register rs);
820 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 820 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
821 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 821 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
822 void bitswap(Register rd, Register rt); 822 void bitswap(Register rd, Register rt);
823 void align(Register rd, Register rs, Register rt, uint8_t bp); 823 void align(Register rd, Register rs, Register rt, uint8_t bp);
824 824
825 // --------Coprocessor-instructions---------------- 825 // --------Coprocessor-instructions----------------
(...skipping 563 matching lines...) Expand 10 before | Expand all | Expand 10 after
1389 public: 1389 public:
1390 explicit EnsureSpace(Assembler* assembler) { 1390 explicit EnsureSpace(Assembler* assembler) {
1391 assembler->CheckBuffer(); 1391 assembler->CheckBuffer();
1392 } 1392 }
1393 }; 1393 };
1394 1394
1395 } // namespace internal 1395 } // namespace internal
1396 } // namespace v8 1396 } // namespace v8
1397 1397
1398 #endif // V8_ARM_ASSEMBLER_MIPS_H_ 1398 #endif // V8_ARM_ASSEMBLER_MIPS_H_
OLDNEW
« no previous file with comments | « src/compiler/mips64/instruction-selector-mips64.cc ('k') | src/mips64/assembler-mips64.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698