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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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87 V(Mips64Lwc1) \ | 87 V(Mips64Lwc1) \ |
88 V(Mips64Swc1) \ | 88 V(Mips64Swc1) \ |
89 V(Mips64Ldc1) \ | 89 V(Mips64Ldc1) \ |
90 V(Mips64Sdc1) \ | 90 V(Mips64Sdc1) \ |
91 V(Mips64BitcastDL) \ | 91 V(Mips64BitcastDL) \ |
92 V(Mips64BitcastLD) \ | 92 V(Mips64BitcastLD) \ |
93 V(Mips64Float64ExtractLowWord32) \ | 93 V(Mips64Float64ExtractLowWord32) \ |
94 V(Mips64Float64ExtractHighWord32) \ | 94 V(Mips64Float64ExtractHighWord32) \ |
95 V(Mips64Float64InsertLowWord32) \ | 95 V(Mips64Float64InsertLowWord32) \ |
96 V(Mips64Float64InsertHighWord32) \ | 96 V(Mips64Float64InsertHighWord32) \ |
| 97 V(Mips64Float64Max) \ |
| 98 V(Mips64Float64Min) \ |
| 99 V(Mips64Float32Max) \ |
| 100 V(Mips64Float32Min) \ |
97 V(Mips64Push) \ | 101 V(Mips64Push) \ |
98 V(Mips64StoreToStackSlot) \ | 102 V(Mips64StoreToStackSlot) \ |
99 V(Mips64StackClaim) \ | 103 V(Mips64StackClaim) \ |
100 V(Mips64StoreWriteBarrier) | 104 V(Mips64StoreWriteBarrier) |
101 | 105 |
102 | 106 |
103 // Addressing modes represent the "shape" of inputs to an instruction. | 107 // Addressing modes represent the "shape" of inputs to an instruction. |
104 // Many instructions support multiple addressing modes. Addressing modes | 108 // Many instructions support multiple addressing modes. Addressing modes |
105 // are encoded into the InstructionCode of the instruction and tell the | 109 // are encoded into the InstructionCode of the instruction and tell the |
106 // code generator after register allocation which assembler method to call. | 110 // code generator after register allocation which assembler method to call. |
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117 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 121 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
118 V(MRI) /* [%r0 + K] */ \ | 122 V(MRI) /* [%r0 + K] */ \ |
119 V(MRR) /* [%r0 + %r1] */ | 123 V(MRR) /* [%r0 + %r1] */ |
120 | 124 |
121 | 125 |
122 } // namespace compiler | 126 } // namespace compiler |
123 } // namespace internal | 127 } // namespace internal |
124 } // namespace v8 | 128 } // namespace v8 |
125 | 129 |
126 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 130 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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