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Issue 1419753008: MIPS: [turbofan] Properly implement Float64/32 Min/Max instructions. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 61 matching lines...)
72 V(MipsLw) \ 72 V(MipsLw) \
73 V(MipsSw) \ 73 V(MipsSw) \
74 V(MipsLwc1) \ 74 V(MipsLwc1) \
75 V(MipsSwc1) \ 75 V(MipsSwc1) \
76 V(MipsLdc1) \ 76 V(MipsLdc1) \
77 V(MipsSdc1) \ 77 V(MipsSdc1) \
78 V(MipsFloat64ExtractLowWord32) \ 78 V(MipsFloat64ExtractLowWord32) \
79 V(MipsFloat64ExtractHighWord32) \ 79 V(MipsFloat64ExtractHighWord32) \
80 V(MipsFloat64InsertLowWord32) \ 80 V(MipsFloat64InsertLowWord32) \
81 V(MipsFloat64InsertHighWord32) \ 81 V(MipsFloat64InsertHighWord32) \
82 V(MipsFloat64Max) \
83 V(MipsFloat64Min) \
84 V(MipsFloat32Max) \
85 V(MipsFloat32Min) \
82 V(MipsPush) \ 86 V(MipsPush) \
83 V(MipsStoreToStackSlot) \ 87 V(MipsStoreToStackSlot) \
84 V(MipsStackClaim) \ 88 V(MipsStackClaim) \
85 V(MipsStoreWriteBarrier) 89 V(MipsStoreWriteBarrier)
86 90
87 91
88 // Addressing modes represent the "shape" of inputs to an instruction. 92 // Addressing modes represent the "shape" of inputs to an instruction.
89 // Many instructions support multiple addressing modes. Addressing modes 93 // Many instructions support multiple addressing modes. Addressing modes
90 // are encoded into the InstructionCode of the instruction and tell the 94 // are encoded into the InstructionCode of the instruction and tell the
91 // code generator after register allocation which assembler method to call. 95 // code generator after register allocation which assembler method to call.
(...skipping 10 matching lines...)
102 #define TARGET_ADDRESSING_MODE_LIST(V) \ 106 #define TARGET_ADDRESSING_MODE_LIST(V) \
103 V(MRI) /* [%r0 + K] */ \ 107 V(MRI) /* [%r0 + K] */ \
104 V(MRR) /* [%r0 + %r1] */ 108 V(MRR) /* [%r0 + %r1] */
105 109
106 110
107 } // namespace compiler 111 } // namespace compiler
108 } // namespace internal 112 } // namespace internal
109 } // namespace v8 113 } // namespace v8
110 114
111 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 115 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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« src/compiler/mips/code-generator-mips.cc ('K') | « src/compiler/mips/code-generator-mips.cc ('k') | src/compiler/mips/instruction-selector-mips.cc » ('j') | src/compiler/mips64/code-generator-mips64.cc » ('J')

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