Re-assign registers on ARM so PP and CODE_REG are below R7 (FP on iOS).

runtime/vm/instructions_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/constants_arm.h"
 #include "vm/cpu.h"
@@ skipping 47 matching lines @@
 
   Register reg;
   uword native_function_load_end =
       InstructionPattern::DecodeLoadWordFromPool(end_ - 2 * Instr::kInstrSize,
                                                  &reg,
                                                  &target_code_pool_index_);
   ASSERT(reg == CODE_REG);
   InstructionPattern::DecodeLoadWordFromPool(native_function_load_end,
                                              &reg,
                                              &native_function_pool_index_);
-  ASSERT(reg == R5);
+  ASSERT(reg == R9);
 }
 
 
 RawCode* NativeCallPattern::target() const {
   return reinterpret_cast<RawCode*>(
       object_pool_.ObjectAt(target_code_pool_index_));
 }
 
 
 void NativeCallPattern::set_target(const Code& new_target) const {
@@ skipping 94 matching lines @@
 // sequence is the instruction before the one at end).  Returns a pointer to
 // the first instruction in the sequence.  Returns the register being loaded
 // and the index in the pool being read from in the output parameters 'reg'
 // and 'index' respectively.
 uword InstructionPattern::DecodeLoadWordFromPool(uword end,
                                                  Register* reg,
                                                  intptr_t* index) {
   uword start = end - Instr::kInstrSize;
   int32_t instr = Instr::At(start)->InstructionBits();
   intptr_t offset = 0;
-  if ((instr & 0xffff0000) == 0xe5990000) {  // ldr reg, [pp, #+offset]
+  if ((instr & 0xffff0000) == (0xe5950000 | (PP << 16))) {
+    // ldr reg, [pp, #+offset]
     offset = instr & 0xfff;
     *reg = static_cast<Register>((instr & 0xf000) >> 12);
   } else {
     ASSERT((instr & 0xfff00000) == 0xe5900000);  // ldr reg, [reg, #+offset]
     offset = instr & 0xfff;
     start -= Instr::kInstrSize;
     instr = Instr::At(start)->InstructionBits();
-    if ((instr & 0xffff0000) == 0xe2890000) {  // add reg, pp, operand
+    if ((instr & 0xffff0000) == (0xe2850000 | (PP << 16))) {
+      // add reg, pp, operand
       const intptr_t rot = (instr & 0xf00) >> 7;
       const intptr_t imm8 = instr & 0xff;
       offset += (imm8 >> rot) | (imm8 << (32 - rot));
       *reg = static_cast<Register>((instr & 0xf000) >> 12);
     } else {
-      ASSERT((instr & 0xffff0000) == 0xe0890000);  // add reg, pp, reg
+      ASSERT((instr & 0xffff0000) == (0xe0800000 | (PP << 16)));
+      // add reg, pp, reg
       end = DecodeLoadWordImmediate(end, reg, &offset);
     }
   }
   *index = ObjectPool::IndexFromOffset(offset);
   return start;
 }
 
 
 RawICData* CallPattern::IcData() {
   if (ic_data_.IsNull()) {
     Register reg;
     InstructionPattern::DecodeLoadObject(ic_data_load_end_,
                                          object_pool_,
                                          &reg,
                                          &ic_data_);
-    ASSERT(reg == R5);
+    ASSERT(reg == R9);
   }
   return ic_data_.raw();
 }
 
 
 RawCode* CallPattern::TargetCode() const {
   return reinterpret_cast<RawCode*>(
       object_pool_.ObjectAt(target_code_pool_index_));
 }
 
@@ skipping 65 matching lines @@
   } else {
     ASSERT(version == ARMv7);
     return bx_lr->InstructionBits() == instruction;
   }
   return false;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM